54 results about "Quadrature oscillator" patented technology

A quadrature oscillator with phase error correction including a local oscillator that generates a single-ended clock signal, a single-ended to differential converter that converts the clock signal to a differential clock signal, a quadrature generator that converts the differential clock signal into I and Q carrier signals, a phase error detector that measures a phase error between the I and Q carrier signals, and a feedback amplifier that modifies the differential clock signal based on measured phase error. The feedback amplifier applies the measured phase error as a DC offset to an AC differential clock signal. A transconductor converts the differential clock voltage signal into two pairs of differential current clock signals, where the quadrature generator generates I and Q current signal outputs from the two pairs of differential current clock signals. The phase error detector generates a phase error voltage, and the feedback amplifier includes a transconductance stage that converts phase error voltage into a DC correction current and that adds the correction current to each of the two pairs of AC differential current clock signals.

A phase error detector that detects phase error between differential signals. A quadrature oscillator provides in-phase (I) and quadrature phase (Q) differential carrier signals and receives a phase error signal from the phase error detector. The oscillator maintains a quarter cycle phase delay between the I and Q carrier signals based on the phase error signal. The phase error detector includes a summing network and first and second bipolar transistor mixer circuits. The summing network develops four sum signals by summing respective pairs of the differential components of the I and Q carrier signals. A bias circuit biases the transistors to turn on at positive base voltages. The mixer circuits may include filter capacitors so that the transistors are responsive to positive base voltages. The mixer circuits develop polarity signals based on the sum signals, and the resulting phase error signal is the differential of the polarity signals.

A quadrature oscillator includes a master tuned oscillator and two injection-locked slave tuned oscillators.

Briefly, devices and methods for tuning of quadrature oscillators which may be used, for example, in a Complementary Metal-Oxide Semiconductor (CMOS) process. Devices and methods in accordance with some exemplary embodiments of the invention may allow, for example, improved locking, tuning and performance of slave oscillators and a master oscillator within a quadrature oscillator utilizing injection-locking.

A circuit provides a reduced harmonic content output signal OUTA and/or OUTB that is modulated according to an input signal 231. The circuit has an oscillator circuit 210 and a harmonic rejection mixer (HRM) 230. The oscillator circuit 210 includes at least one “circuit portion” (FIG. 2A) configured to receive first and second orthogonal oscillator input signals (two of I, I-, Q, Q-) having respective first and second phases, and to provide an arbitrarily large number of oscillator output signals (φM) having respective mutually distinct phases that are interpolated between the first and second phases. Harmonic rejection mixer 230 is configured to use the input signal to modulate a combination of the oscillator output signals, the oscillator output signals being respectively weighted so as to provide an emulated sinusoidal signal constituting the reduced harmonic content output signal.

In wireless application there is made use of a quadrature oscillators that generate signals that are capable of oscillating at quadrature of each other. The quadrature oscillator is comprised of two differential modified Colpitts oscillators. A capacitor bank allows for the selection of a desired frequency from a plurality of discrete possible frequencies. The quadrature oscillator is further coupled with a phase-error detector connected at the point-of-use of the generated ‘I’ and ‘Q’ channels and through the control of current sources provides corrections means to ensure that the phase shift at the point-of-use remains at the desired ninety degrees.

Nth-order voltage- and current-mode arbitrary phase shift oscillator structures are synthesized using n operational trans-conductance amplifiers (OTAs) or second-generation current controlled conveyors (CCCIIs) and n grounded capacitors. Linking up the I/O characteristics of the OTA and the CCCII and the reactance of grounded capacitor, the step of synthesis is first based on the algebraic analysis to oscillatory characteristic equations, resulting in a quadrature oscillator structure. Secondly, instead of the quadrature characteristic, to control each output signal with one another by a desired phase difference > or <90°, selectively superposing any of two fundamental OTA/CCCII-C sub-circuitries benefits the transformation of quadrature to arbitrary-phase-shift characteristic for the sinusoidal oscillator structure. Furthermore, several compensation schemes are presented for reducing the output parameter deviation due to the non-ideal effects.

Circuits and methods and for generating oscillator outputs using standard integrated circuit components. The basic circuit generally includes two inverters and a variable capacitor to configure a delay of the circuit input and/or output. The oscillator circuit generally includes a plurality of inverter circuits, at least one of which uses a variable capacitor to adjust a delay between stages, and thereby adjust a frequency of oscillation. Thus, the oscillator outputs may be tuned using a single control voltage. The method generally includes the steps of (1) applying an operating voltage to a ring oscillator comprising a plurality of stages; and (2) applying a control voltage to a variable capacitor coupled to a node between at least two of those stages. The circuits have particular advantage in quadrature oscillators, and may be easily implemented using widely available CMOS technology.

The invention discloses a reconfigurable multi-frequency-range transceiver radio-frequency front end which comprises a receiver part, a transmitter part and a frequency synthesizer, wherein the receiver part comprises a low-noise amplifier, a first-stage reconfigurable lower frequency converter, a second-stage orthogonal lower frequency converter and a first medium-frequency circuit which are sequentially connected; the first medium-frequency circuit is connected with a digital baseband modem; the transmitter part comprises a second medium-frequency circuit, a first-stage low-frequency upper frequency converter, a second-stage high-frequency upper frequency converter and a power amplifier; the second medium-frequency circuit is connected with the digital baseband modem; the frequency synthesizer comprises a phase lock ring; a frequency output of the phase lock ring is connected with the first-stage reconfigurable lower frequency converter, an orthogonal oscillator and a multi-phase filter; the orthogonal oscillator is connected with the second-stage orthogonal lower frequency converter and the first-stage low-frequency upper frequency converter; and an output of the multi-phase filter is connected with the second-stage high-frequency upper frequency converter. According to a reconfiguration method, a zero medium-frequency structure and a sliding medium-frequency structure are synthesized, so that the performance of a transceiver is improved, and the power consumption of the transceiver is reduced.

Briefly, exemplary embodiments of the invention may provide devices and methods to provide precise and/or low phase-noise quadrature oscillation signals. A quadrature oscillator in accordance with an exemplary embodiment of the invention may include, for example, a phase-shift generator to provide a phase-shift of substantially π/2 radians to an oscillation signal between a first oscillation tank, which provides substantially no phase-shift, and a second oscillation tank.

The invention belongs to the technical field of radio frequency wireless transmitter/receiver integrated circuits, and particularly relates to a low-phase-noise quadrature voltage-controlled oscillator which can be applied to the wireless transmitter/receiver integrated circuits. The low-phase-noise quadrature voltage-controlled oscillator is composed of two LC voltage-controlled oscillators, two pairs of capacity coupling pipes and split-conversion offset pipes. Through the split-conversion-offset technology and the capacity-coupling technology, a novel quadrature voltage-controlled oscillator circuit is designed, compared with a traditional quadrature voltage-controlled oscillator, the novel circuit is added with output swings, 1/f noise is lowered, and phase noise is lowered. The quadrature voltage-controlled oscillator has the advantages of being low in phase noise, simple in structure, small in chip area, and the like.

The present invention relates to an oscillator circuit and a method of controlling the oscillation frequency of an in-phase signal and a quadrature signal. First oscillator means (2) with a first differential oscillator circuit and a first differential coupling circuit are provided for generating the quadrature signal. Furthermore, second oscillator means (4) with a second differential oscillator circuit and a second differential coupling circuit are provided for generating the in-phase signal. A frequency control means is provided for varying the oscillation frequency of the in-phase signal and the quadrature signal by controlling at least one of a common-mode current and a tail current of the first and second oscillator means. Thereby, a high-frequency IQ oscillator with high linearity is obtained.