155 results about "Hardware reset" patented technology

Methods, systems and computer program products which provide secure updates of firmware (i.e. data stored in a programmable memory device of a processing system) are disclosed. Updates of a programmable memory of a device may be controlled by providing an update window of finite duration during which the programmable memory may be updated. Access to the programmable memory may be based on the state of an access latch. The access latch may be set to allow access after a hardware reset of the device. An update control program may be executed to control access to the programmable memory and the latch reset to prevent access upon completion of the update control program. Verification of the update may be provided through encryption techniques and rules incorporated in certificates for application of updates to provide for selectively updating devices. Also disclosed are methods of securely providing differing functionality to generic devices.

The invention discloses a comprehensive fault detecting device and a method for shifting a main computer and a standby computer, and relates to the application communication field. The invention aims at providing comprehensive detection in main-standby shifting condition. The main computer and the partner computer of a main-standby shifting comprehensive fault detecting device are symmetric in structures. Each of the main computer and the partner computer respectively includes a CPU, a programmable control circuit module which is connected with the CPU through a CPU address / data / control bus, a communication interface module, a hardware reset register, and a software reset register; the programmable control circuit module contains a summation meter inside. A main-standby shifting comprehensive fault detecting method includes the steps of initializing a programmable control circuit and the application software; conducting state detection and data synchronization on the main computer and the partner computer periodically, and determining whether a mark in the hardware reset register and the software reset register is read according to the detection result. The invention is applicable for an important working unit which needs the communication and control bus distribution system with main-standby shifting function.

The invention provides a circuit with an automatic power-off restarting function in equipment failure. A CPU of the equipment is connected with a key device of the equipment and the CPU is capable of monitoring the working state of the key device; when the equipment has hardware damage-free failure, the CPU stops outputting a feeding-dog signal, a watchdog circuit does not trigger the system hardware reset any more, and outputs a power switch control signal; a power switch circuit turns off the direct-current power supply of the equipment after being triggered; and after certain time delay, the power switch circuit automatically starts the direct-current power supply of the equipment to ensure that the equipment is restarted to restore the normal work. According to the circuit provided by the invention, the failure problems of all the hardware damage-free units can be solved; no matter whether the units with failures have hardware reset functions or not, the adopted power-off restarting manner is more thorough than the traditionally adopted hardware reset manner.

A boot up method makes an electronic system boot up by a processor according to a boot code in a NAND flash memory and includes the following steps. First, the flash memory storing a boot code or boot codes is provided. Next, a first boot code is copied to an XIP memory in response to a hardware reset signal. Then, the processor executes the first boot code in the XIP memory and thus makes the system boot up. Next, whether the system boots up successfully is judged after a time delay. When the system fails to boot up, the system is reset and a second boot code is copied to the XIP memory. Thereafter, the processor executes the second boot code in the XIP memory and thus boots up the system. If the system still fails to boot up, the above-mentioned steps are repeated until the system boots up successfully.

Each data storage device that supports the standard security features and is enabled with a security password may be locked when power is removed from the device. When power is returned, a determination is made as to whether the data storage device is locked and returning from a powered off state or a hardware reset. If locked, a password may be received from a user. After the security password is received, the data storage device is unlocked, allowing access to the data on the device. A setup utility is provided for manipulating the security and backup passwords for each device. Other features include: presenting locked devices to the operating system, the use of a backup password to unlock a device in lieu of the security password, requiring or not requiring password entry from a user to unlock a device when returning from a sleep state, setting maximum or high security, an automatic hardware reset upon exiting the setup utility, and disabling change password capabilities for devices without an enabled security password.

A bridge system having at least one bridge chip to control the operations of the bridge. Each bridge chip uniquely connects to a bus interface allowing communications between a host system and the bridge chip when that bus interface is to be utilized. Each bridge chip also connects to another bus interface connecting the bridge with a device. Each bridge chip includes an activation circuit that automatically disables that bridge chip after a power-on or a hardware reset occurs. When the activation circuit receives a protocol initialization signal, the activation circuit causes only the associated bridge chip to become enabled. Once enabled, the bridge chip drives all of the pins in the bus interface connecting the bridge with the device and remains in control of that bus interface until a power-off, a hardware reset occurs, or the bridge chip has been physically disconnected from the host.

A booting method capable of executing a warm boot or a cold boot when a CPU crash occurs in a computer system having a CPU and a memory. First, when the CPU is in a crash state, it is detected that a user wants to execute a hardware reset function or a software reset function. Next, a hardware reset operation is executed to reboot the CPU. Then, when the user chooses to execute the hardware reset function, data and predefined values of the memory are deleted to make the computer system return to a default state. Thereafter, when the user chooses to execute the software reset function, the hardware reset operation is regarded as an operation to replace a software reset operation, and the computer system holds the data and predefined values to make the computer system return to a setting state before the computer system is crashed.