64 results about "Front-side bus" patented technology

Method and apparatus to enable I / O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I / O agents that issue atomic transactions to access and / or modify data stored in a shared memory space accessed via the memory interface unit. The host interface unit interfaces to a front-side bus (FSB) to which one or more processors may be coupled. In response to an atomic transaction issued by an I / O agent, the transaction is forked into two interdependent processes. Under one process, an inbound write transaction is injected into the host interface unit, which then drives the FSB to cause the processor(s) to perform a cache snoop. At the same time, an inbound read transaction is injected into the memory interface unit, which retrieves a copy of the data from the shared memory space. If the cache snoop identifies a modified cache line, a copy of that cache line is returned to the I / O agent; otherwise, the copy of the data retrieved from the shared memory space is returned.

Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set operational parameters of the PCIe endpoints so as to maximize usage of the available bandwidth of a front-side bus while minimizing isochronous issues and the likelihood that the performance of the PCIe endpoints cannot be guaranteed. A first table data structure comprises various combinations of operational parameter settings for controlling bandwidth usage of each of the endpoints of the data processing system. A second table data structure contains a listing of the endpoints that the data processing system supports with their associated minimum data rates, priorities, and whether the endpoints have isochronous requirements. A setting of the desired bandwidth balancing level is used along with these data structures to determine how to adjust the operating parameters of the PCIe endpoints.

A method for dynamically adjusting central processing unit (CPU) frequency. Firstly, a translation table is provided between multi-layer of CPU usage percentage and front-side bus operation frequency. Secondly, a current usage percentage of the CPU is obtained. Lastly, the operation frequency of the front-side bus is adjusted to a corresponding layer according to the current usage rage, so that the current usage rage is located within the range of CPU usage percentage that is defined by corresponding layer.

The invention provides a time sequence control circuit, which is used for providing a time sequence control signal for a front-end bus power supply of a computer. The time sequence control circuit comprises an electronic switch and two voltage-sharing resistors, wherein the two voltage-sharing resistors are connected in series with each other and are connected to a system power supply and grounded respectively; the time sequence control signal is output between the two voltage-sharing resistors; the first end of the electronic switch is electrically connected with the two voltage-sharing resistors, and the second end of the electronic switch is electrically connected to a control signal end of the computer; and the level of the control signal end and the level of the time sequence control signal are set at the same phase. The invention also relates to a front-end bus power supply with the time sequence control circuit.

By adjusting a scale factor of a phase locked loop in computers for generating a basic clock signal of a front-side bus, the frequency of the basic clock signal is modulated when the central processing unit of computers operates. By a bridge unit of the present invention, a selecting signal is received so as to output a corresponding adjustment signal to a check unit and then the check unit checks the adjustment signal for outputting a checking signal to a scale parameter adjustment unit. According to the checking signal, the scale parameter adjustment unit adjusts a first scale parameter of the scale factor that the phase locked loop uses now and outputs this parameter to the phase locked loop. Thus after receiving a fixed clock signal for generating the basic clock signal, the phase locked loop generates the basic clock signal of the front-side bus in accordance with the adjusted first scale parameter and further the frequency of the basic clock signal is adjusted.

A switching circuit located in a computer system is disclosed in the present invention. The switching circuit comprises a first phase-locked loop generating a first host clock signal, a second phase-locked loop generating a second host clock signal and an output switch unit coupled to the first PLL and the second PLL. When the computer system operates in a first mode, the output switch unit chooses the first host clock signal to be a fundamental clock signal of the front side bus. In the other hand, when the computer system operates in a second mode, the output switch unit chooses the second host clock signal to be a fundamental clock signal of the front side bus.

In a dynamic mode, firmware sets a threshold of errors that may occur within a predetermined period of time. If the threshold is exceeded, the firmware queries the front-side bus performance counters to determine whether the front-side bus is operating at its maximum data rate. If the front-side bus is not running at the maximum data rate, then the firmware bumps the data rate settings for the endpoint that exceeds the threshold by one step. If the front-side bus is running at its maximum data rate, then the firmware queries all the endpoints to determine which endpoints are active. The firmware then determines whether there are any active endpoints that are lower priority than the complaining endpoint. The mechanism drops the lower priority endpoints by one step and raises the complaining endpoint by one step.

A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

A portion of chip die real estate is allocated to blocks of programmable logic (PL) fabric. These blocks can be used to load special purpose processors which operate in concert with the general purpose processors (GPPs). These processors, implemented in PL, may integrate with a PC system architecture. Blocks of PL are integrated with fixed blocks of logic interfaces connecting, for example, to a system's front side bus. This facilitates configuration of the PL as coprocessors or other devices that may operate as peers to GPPs in the system. Moreover, blocks of PL may be integrated with fixed logic interfaces to existing IO buses within a system architecture. This facilitates configuration of the PL as soft devices, which may appear to the system as physical devices connected to the system. These soft devices can be handled like physical devices connected to the same or similar IO buses.

A method for overclocking a central processing unit (CPU) of a computer motherboard is disclosed. Step A is to set a second frequency of front side bus (FSB) by an operating interface of BIOS. Step B is to determine FSB frequency Fn at each of N stages according to a difference between a first frequency and the second frequency. Step C is to load the CPU with an operating system by booting the CPU at the first frequency of FSB, and send an interruption signal to the CPU from a chipset at predetermined intervals upon completion of the loading of the operating system so as to allow the BIOS to gain control over the CPU, and execute step D by the CPU on each of N occasions of interruption until the FSB frequency of the CPU is changed to the second frequency. Step D is to execute the BIOS by the CPU on the nth occasion of interruption such that the CPU operates at the FSB frequency Fn, and allow the operating system to resume control over the CPU.