84results about How to "Reduced voltage swing" patented technology

A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (ΔVbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (ΔVbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue−Vref or 2×Vresidue+Vref.

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe and also a write data strobe that is out-of-phase relative to the read data strobe, and presents data synchronously with one of the edges of that read data strobe. In the advanced mode for a data write, the input data is presented by the controller synchronously with a selected edge of both the write data strobe and the read data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

A display device (500) is described with a plurality of pixels (555), each having a pixel state (P) that is driven by a driving voltage differential (V_EP) between a pixel voltage (V_px) applied to a pixel terminal (101) of the pixel and a common voltage (V_CE) applied to a common terminal (102) of the pixel. In a first pixel driving state, wherein pixels are driven to a first colour, a common voltage is provided to the common terminals (102) with a first polarity. In a second pixel driving state, wherein pixels are driven to a second colour, a common voltage is provided to the common terminals (102) with a second polarity opposite to the first polarity. An absolute value of the common voltage (V_CE) in the first and second pixel driving state is higher than a maximum absolute value of the column voltage (V_col) in the corresponding pixel driving state.

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe and also a write data strobe that is out-of-phase relative to the read data strobe, and presents data synchronously with one of the edges of that read data strobe. In the advanced mode for a data write, the input data is presented by the controller synchronously with a selected edge of both the write data strobe and the read data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

The invention discloses a current switching circuit for a high-speed current rudder digital-to-analog converter, comprising a switch main body circuit, a constant-current circuit which provides a constant flow source for the switch main body switch, a switch drive circuit which provides difference switching signals to the switch main body circuit and a four-phase control signal generating circuit which provides difference control signals for the switch drive circuit. A pre-breakover pull-down MOS (Metal Oxide Semiconductor) tube is adopted in the switch drive circuit , and a clock feedthrough compensation structure is applied to the switch main body circuit, thus overshooting of the difference switching signals is greatly weakened, falling edges of the difference switching signals at the initial stage of hopping become gentle, symmetry of rising and falling edges of the difference switching signals in case of low swing amplitude is improved and clock feedthrough errors resulting from the difference switching signals are effectively reduced. The current switching circuit is especially applicable to the high-speed and high-precision digital-to-analog converter.

A display and a two step driving method thereof are provided. The method includes: converting an image signal to a corresponding data driving voltage by using a driver; providing a pre-driving voltage by using a voltage generator; and finally, driving the display panel by using the pre-driving voltage and data driving voltage orderly during a horizontal synchronizing period. A display includes a display panel, a voltage generator, and a driver. The display panel also includes at least one data line. The voltage generator outputs a pre-driving voltage to the data line of the display. The driver outputs a data driving voltage to the data line according to an image signal, in which the data line receives the pre-driving voltage and the data driving voltage orderly during the horizontal synchronizing period.

A driving method of liquid crystal display. Voltage levels of pre-charging signals applied to storage electrodes vary before scan signals are applied to scan lines. Partial response voltage of the variations in voltage levels of pre-charging signals are respectively coupled to storage capacitors within pixels by capacitors. When the scan signals are applied to the scan lines, voltage swings of the pixel capacitors charged by image data on data lines decrease, rapidly charging the pixels.

An apparatus is disclosed that may reduce the dynamic power dissipation of a configurable IC device such as an FPGA by reducing the peak-to-peak voltage swing of signals transmitted over the device's interconnect signal lines without including additional level shifter circuits. For some embodiments, existing multiplexing circuit architectures provided within logic resources of various logic blocks of the configurable IC device may be used as level shifter circuits to increase the voltage swing of signals received into the blocks from the interconnect signal lines, and modified multiplexing circuit architectures provided within the logic resources may be used to reduce the voltage swing of signals output from the logic blocks onto the interconnect signal lines.

A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

An output buffer and a source driver for a display panel are provided. The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage. The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal. The bias module provides a bias current to the differential input stage. The output stage has a second output terminal coupled to the first input terminal for providing an output current to the second output terminal based on a signal of the first output terminal. The feedback module adjusts the bias current and the output current based on the first input signal and the second input signal. The output buffer has ability of switching the output voltage to be low level and high level in high-speed.