65 results about "Memory scrubbing" patented technology

A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubbing controller then detects any errors in the read error correcting codes, and generates corrected error correcting codes that are written to the DRAM. This scrubbing procedure, by reading error correcting codes from the DRAM, inherently refreshes memory cells in the DRAM. The error correcting codes are read at rate that may allow data errors to be generated, but these errors are corrected in the memory scrubbing procedure. However, the low rate at which the error correcting codes are read results in a substantial power saving compared to refreshing the memory cells at a higher rate needed to ensure that no data errors are generated.

Embodiments of the invention include a memory device, such as a removable expanded memory card, having a host bus interface that allows a host to access a memory of the device. The memory device also includes memory scrubbing circuitry to read data stored at addresses in the memory and to identify single-bit errors and multiple-bit errors in the data read from the memory.

Systems and methods for improving scrubbing techniques are provided. In one aspect, the error correction code for a memory line is strengthened by reorganizing the memory line into distinct portions and providing an error code set that includes a distinct error code for each portion of the memory line. In another aspect of the invention, the scan rate is effectively increased by moving memory scrubbing functionality into the memory system and distributing it among a number of subcomponents that can operate scrubbing functions in parallel. The effective scan rate increase reduces the probability of failure for any given ECC strength.

A method and apparatus for coordinating dynamic memory page deallocation with a redundant bit line steering mechanism are provided. With the method and apparatus, memory scrubbing and redundant bit line steering operations are performed in parallel with handling of notifications of runtime correctable errors. When a correctable error is encountered during runtime, and the correctable error is determined to be persistent, then dynamic memory page deallocation is requested of a hypervisor. The determination of persistence is based on a history CE table that is populated by the operation of the memory scrubbing and redundant bit line steering mechanism of a service processor. Thus, only those correctable errors that persist for longer than one memory scrubbing cycle are subject to memory page deallocation.

A schedulable memory scrubbing circuit and/or a known-state memory test circuit (collectively, background memory test apparatus (“BGMTA”)) are located on-chip with an integrated computing system. The BGMTA operates in parallel with a system CPU but shares a system bus with the CPU. The BGMTA sequentially reads one word at a time from a block of memory to be tested during system bus idle cycles. The schedulable memory scrubbing circuit embodiment tests on-chip parity/ECC memory arrays using memory controller-implemented parity or ECC error detection to trigger error handling interrupts. The known-state memory test circuit embodiment performs CRC calculations on known-state memory arrays as each data word is read sequentially. A final resulting CRC calculation value is compared to a known CRC value for the block, sometimes referred to as a “golden CRC.” If the two CRC values differ, a CRC error interrupt is triggered for servicing by the CPU.

A data processing apparatus is provided which comprises a processor unit configured to perform data processing operations in response to a sequence of instructions and a storage unit configured to store data values for access by the processor unit when performing its data processing operations. Redundant error control data is stored in association with the data values, the redundant error control data enabling identification of an error in the data values. The data processing apparatus also comprises a data scrubbing unit configured to perform a data scrubbing process on at least a subset of the data values, the data scrubbing process comprising determining with reference to the redundant error control data if an error is present in that subset of data values and, where possible, correcting that error with reference to the redundant error control data. The data scrubbing unit is configured to receive a scrub transaction issued within said data processing apparatus, and to perform the data scrubbing process upon receipt of the scrub transaction.

The invention relates to the field of memories and provides a memory cleaning method and a memory cleaning device for video playback equipment. The video playback equipment is in communication connection with mobile communication terminal equipment in advance on the side of the mobile communication terminal equipment. The method comprises the following steps: providing a user operation entrance in a user interface of the mobile communication terminal equipment; receiving a request for cleaning the memory of the video playback equipment transmitted by a user through the user operation entrance; transmitting a memory cleaning command to the video playback equipment through the communication connection, so that the video playback equipment executes the memory cleaning operation according to the memory cleaning command. According to the method, a phenomenon that lots of memory space is occupied by unimportant programs is avoided, and the operating speed of the whole system is improved.

A method for updating a DRAM memory array is disclosed. The method comprises: a) receiving a command from a memory controller to initiate an active cycle for activating a memory row in a DRAM memory array; b) performing an Error Correction Code (ECC) scrub on the memory row prior to reading data from the memory row into sense amplifiers in the DRAM memory array in accordance with the command to activate; c) activating the memory row; and d) writing corrected data following the ECC scrub back into memory from the sense amplifiers during a pre-charge cycle of the DRAM memory array.

A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.

The invention discloses a control method, circuit and system for reducing standby power consumption of a computer mainboard. The system comprises a processor, a user interface and a memory, and the control circuit comprises a current monitoring module, a calculation and analysis module, a standby power supply and a processing module. The method comprises the following steps: firstly, monitoring acurrent input end and a current output end of a computer mainboard in real time, performing calculation and analysis according to the monitored current values, when an abnormal judgment result is output, changing current input of the computer mainboard, closing operation of a program connected with the computer mainboard, performing memory cleaning and backup on the computer mainboard, and adjusting the brightness of a display screen or closing the display screen. The current input of the computer mainboard can be converted in real time according to the output judgment result, so that the standby state of the computer mainboard can be conveniently controlled, and the standby power consumption of the computer mainboard can be effectively reduced.

A data processing apparatus includes a memory and memory protection circuitry for providing an operational path to the memory during operational use of the memory. A memory built-in self-test controller 34 performs built-in self-test operations upon the memory using either an indirect test access path to the memory via the memory protection circuitry or a direct test access path to the memory which bypasses the memory protection circuitry. Thus, the correct operation of the memory protection circuitry itself can be tested in addition to the correct operation of the memory.

The invention relates to a method and device for automatically cleaning memory, electronic equipment and a storage medium, and the method comprises the steps: determining a file meeting a preset expiration condition as an expiration file in files of an application stored in a terminal; when the residual space of the terminal is smaller than a preset threshold value, screening out an expired file meeting a preset cleaning condition from the expired files as a to-be-deleted file; and deleting the to-be-deleted file. According to the technical scheme provided by the invention, the file meeting the condition is used as the expired file; deleting the to-be-deleted files in the expired files when the residual space of the terminal is smaller than a preset threshold value; compared with the priorart that a user needs to manually delete the files, the method has the advantages that the expired files are searched out firstly, and then the unnecessary files are automatically deleted when the residual space of the terminal is insufficient, so that the memory can be automatically cleaned, other memory cleaning software does not need to be downloaded, the operation process of the user is reduced, and the memory cleaning efficiency is improved.

Mirrored memory scrubbing is optimized to reduce system power consumption and increase system performance. A memory scrub operation scrubs a first portion of the mirrored memory to detect and correct soft errors. The scrub rate of a second portion of the mirrored memory is eliminated, minimized, or reduced, relative to the scrub rate of the first portion. The reduced scrub operation preserves power consumed in association with scrubbing the second portion.

The invention provides a track flow data-oriented continuous range query method and system. The system comprises a position information sending module, an index module and a query module. According to the invention, an index module is improved firstly, it can be guaranteed that track points are rapidly inserted according to the spatial positions and the time sequence of the track points, and ID-time range query and spatial range query of tracks are supported. Thirdly, a query module is improved, an internal and external memory combined query mechanism is adopted, and the number of times of spatial intersection judgment and the number of times of data needing to be retrieved are reduced to the maximum extent; and furthermore, an index module and a query module are supplemented, so that the query accuracy can be ensured under the condition that the query is changed. Finally, a memory cleaning module is further included, when the number of query times and the number of concurrent queries are increased, a result set is reduced, and the memory burden is relieved. According to the invention, under the condition of ensuring real-time updating of data, time range query and space range query are realized at the same time, and the efficiency of continuous range query is improved.

A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).