Flash memory structure and its preparation method

Abstract

The invention relates to a quick flash memory unit, which is based on the vertical-channel fieldistor. It is characterized in that: the n+ doping area above the silicon base is the source; the n+ doping area at the two sides of silicon base are leak ends; the each side of silicon base has two multi-silicon grids, while the outer multi-silicon grid is the control grid and the inner multi-silicon grid is the float grid; the spaces between the float grid and the channel area and the source area are the tunnel oxygenation layers; the spaces between the control grid and the channel area and the float grid are the baffle oxygenation layers; the n+ leak ends at the two sides of silicon base are separated connected to form two memory units sharing the source end. The invention also provides a preparation method of said device, which is characterized in that: it uses the plasma coupling high-selection rate opposite etching technique and the reaction ion hermaphroditic etching technique, to self-position form the separation grid and float grid structures, while the channel length of control grid and the channel length of float grid are both realized by the etching technique.

Description

technical field [0001] The invention belongs to the technical field of non-volatile semiconductor memory, and relates to a flash memory unit and a preparation method thereof, in particular to a flash memory unit with a split gate floating gate structure based on a vertical channel field effect transistor and a preparation method thereof. Background technique [0002] Semiconductor memory is an important part of the semiconductor industry. With the increasing demand for data storage in various mobile devices, the demand for non-volatile semiconductor memory that can still store data in the event of power failure is also increasing. Flash memory (flash memory, referred to as flash memory) is the fastest growing non-volatile semiconductor memory. Since the first flash memory product came out in the 1980s, with the development of technology, it has been widely used in mobile communication devices and personal computers such as mobile phones, notebook computers, handheld computer...

AI Technical Summary

Problems solved by technology

This programming method has a great disadvantage: due to the coupling of the electric field of the drain terminal and the electric field of the gate, only the electric field of the oxide layer near the pinch-off point is conducive to collecting electrons, that is to say, only a small part of the channel pairs near the pinch-off point programming is efficient, so programming is rather inefficient

[0007] However, this kind of planar split gate floating gate memory cell using source-side CHEI programming method also has the following disadvantages: hot electrons entering the depletion region can only reach the gate oxide interface through scattering with a certain probability, and then cross the tunnel oxide layer with a certain probability The utilization efficiency of hot electrons is still low; the minimum area of ​​the flash memory cell can only be 4F×2F=8F 2 (unit area: the dimension in the horizontal direction of the cross-sectional view is 4F, and the dimension perpendicular to the direction of the cross-section is 2F, where F is the feature size of photolithography technology); at the same time, in order to reduce the unit area and increase the integration degree, the device size is continuously reduced Small, the photolithographic alignment of the control gate and floating gate will be very difficult, which brings great difficulties to the process

[0009] However, the split gate flash memory cell of this vertical channel device also has the following disadvantages: 1) The gate length of the control gate is still defined by the optical lithography technology, that is, due to the limitation of the optical lithography technology, the control gate length of the structure is the smallest Only one feature size (F) can be achieved, so the minimum layout area of ​​each flash memory unit can only be 2F×2F=4F 2 (Fig. 4 is a cross-sectional view of a flash memory unit: set the horizontal direction of the cross-sectional view as the X-axis, the depth direction as the Y-axis, and set the direction perpendicular to the cross-section as the Z-axis; the cross-section is the XY plane, and the layout refers to the top-view XZ plane); 2) The split gate floating gate structure is formed by using the side wall gate process, which is a non-self-aligned process, and the deviation of the process will make it difficult to control the coupling capacitance between the floating gate and the control gate; 3 ) For vertical channel split-gate flash memory cells with such a trench gate structure (the gate sidewall is on both sides of the etched trench), the covering capacitance of the source terminal to the floating gate depends on the thickness of the floating gate sidewall, Due to the width limitation of the groove (in order to reduce the unit area, the groove width should be as small as possible, and a contact hole for the source terminal electrode needs to be opened in the groove), the allowable maximum sidewall thickness is limited, so the source terminal to the floating gate The coupling coefficient becomes smaller; under the same source terminal voltage, the floating gate voltage obtained by coupling is relatively small, that is, the ability of the floating gate to collect hot electrons will be reduced, and the injection efficiency will be deteriorated

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