The invention relates to a digital circuit, and discloses a memory optimization type static time sequence analysis method and system. According to the method, on the premise that the subgraphs are notexpanded, in the traversing and scanning process, false paths are identified and discarded in real time, the influence of the false paths on downstream nodes is reduced, redundant calculation is reduced, meanwhile, multiple time sequence constraints on each node are dynamically and differentially processed in the traversing process, dichotomy coverage is correspondingly carried out, and the number of labels on each node is reduced. According to the application, occupation of system memory space can be greatly reduced, the system operation efficiency is improved, and the system performance isimproved.