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Memory-optimized static timing analysis method and system

A static timing analysis and memory technology, applied in the direction of instruments, computing, electrical digital data processing, etc., can solve the problem of large memory consumption, achieve the effect of reducing the number of tags, improving analysis efficiency, and reducing the occupation of memory space

Active Publication Date: 2021-01-05
SHANGHAI ANLOGIC INFOTECH CO LTD
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  • Claims
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Problems solved by technology

The operating efficiency of the underlying engine, including running time and space consumption, becomes the bottleneck of the efficiency of the whole set of tools. The inventors of this application have observed that the most cutting-edge static timing analysis method in the prior art can eliminate false paths and clarify multi-cycle paths. There is a problem with excessive memory consumption

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  • Memory-optimized static timing analysis method and system
  • Memory-optimized static timing analysis method and system

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Embodiment Construction

[0055] In the following description, numerous technical details are set forth in order to provide the reader with a better understanding of the present application. However, those of ordinary skill in the art can understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be realized.

[0056] Explanation of some concepts:

[0057] 1. Static timing analysis: In electronic engineering, the calculation and prediction of the timing of digital circuits are performed. This process does not need to be simulated by input excitation. Traditionally, people often regard the operating clock frequency as one of the characteristics of high-performance integrated circuits. In order to test the ability of a circuit to operate at a specified rate, one needs to measure the delay of the circuit at various stages of operation during the design process. In addition, ...

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Abstract

The invention relates to a digital circuit, and discloses a memory optimization type static time sequence analysis method and system. According to the method, on the premise that the subgraphs are notexpanded, in the traversing and scanning process, false paths are identified and discarded in real time, the influence of the false paths on downstream nodes is reduced, redundant calculation is reduced, meanwhile, multiple time sequence constraints on each node are dynamically and differentially processed in the traversing process, dichotomy coverage is correspondingly carried out, and the number of labels on each node is reduced. According to the application, occupation of system memory space can be greatly reduced, the system operation efficiency is improved, and the system performance isimproved.

Description

technical field [0001] The present application relates to the field of digital circuits, and in particular, to a memory-optimized static timing analysis method and system thereof. Background technique [0002] In the process of physical design implementation of digital circuits, static timing analysis plays a very important role, and its feedback results provide the driving force for multi-pass optimization procedures in this process. , the tools kernel repeatedly invokes the static timing analysis iterative optimization multiple times. Therefore, as a crucial underlying analysis engine, the performance of static timing analysis tools has a very important impact on the performance of the entire software tool. The operation efficiency of the underlying engine, including running time and space consumption, becomes the bottleneck of the efficiency of the whole set of tools. The inventor of the present application has observed that the most advanced static timing analysis metho...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/3312
Inventor 朱春谢丁
Owner SHANGHAI ANLOGIC INFOTECH CO LTD
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