36results about How to "Low ESL" patented technology

A solid electrolytic capacitor includes a cathode including a solid electrolytic layer, an anode, and a dielectric layer provided between the cathode and the anode. The anode includes an anode body, an input anode terminal and an output anode terminal. A bypass current path for causing circuit current to detour around the anode body is formed between the input anode terminal and the output anode terminal.

A multilayered chip capacitor (MLCC) includes internal electrodes and external electrodes formed to be perpendicular to the internal electrodes, whereby parasitic capacitance is reduced, resulting in no parallel resonance frequency effects. In addition, the MLCC has a capacitor structure, which provides a first surface and a second surface formed in a stacking direction of the dielectric layers in the capacitor body as a top surface and a bottom surface. Hence, in the thin capacitors having the same size, the number of internal electrode layers is increased, thereby reducing the equivalent series resistant (ESR) and equivalent series inductance (ESL). Further, the printed circuit board (PCB) having an embedded MLCC is easily manufactured.

In a capacitor body of a multilayer capacitor, one second capacitor portion is sandwiched between two first capacitor portions. An ESR is controlled by setting a width of lead portions of third and fourth internal electrodes disposed in the second capacitor portion to be less than that of lead portions of first and second internal electrodes disposed in the first capacitor portions and by changing ratios between the first and second capacitor portions in the width of the lead portions and in the number of stacked internal electrodes. In the first capacitor portions, current paths from the internal electrodes to an external terminal electrode are widely distributed so that the first capacitor portions have a relatively low ESL, and accordingly, the ESL of the entire multilayer capacitor is reduced.

The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.

A solid electrolytic capacitor includes a capacitor unit having a cathode frame coupled to a cathode part of a capacitor element, and anode frames formed at the opposite sides of the capacitor unit sandwiching a cathode frame, and coupled to an anode part of the capacitor element. Flat parts provided at the opposite ends of anode terminals are coupled to the anode frames. A flat part provided in the center of a cathode terminal is coupled to the cathode frame. The capacitor unit is covered with coating resin. The solid electrolytic capacitor has a simplified structure and a lower ESL.

In a capacitor body, a single second capacitor unit is interposed between two first capacitor units. The width direction dimension of each of extended portions of first and second internal electrodes included in the first capacitor unit is larger than the width direction dimension of each of extended portions of third and fourth internal electrodes included in the second capacitor unit. The area of each of the respective portions of a first opposed portion of the first internal electrode and a second opposed portion of the second internal electrode, the respective portions being opposed to each other, is smaller than the area of each of respective portions of opposed portions of the third and fourth internal electrodes, the respective portions being opposed to each other. Thus, a multilayer capacitor has a characteristic that is a combination of a low-ESL characteristic of the first capacitor unit and a high-ESR characteristic of the second capacitor.

A wound, metallized dielectric film capacitor for pulsed power applications is disclosed. The capacitor forms a wound metallized polymer film in the shape of a closed path ring. The electrical load is placed within the inner opening of the capacitor. The capacitor has low inductance and resistance, scales to high energy levels, and can be formed around the electrical load.

A multilayer chip capacitor including: a capacitor body having a lamination structure where a plurality of dielectric layers are laminated and including a first capacitor part and a second capacitor part arranged according to a lamination direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, the first and third outer electrodes having the same polarity and the second and fourth outer electrodes having the same polarity opposite to that of the first outer electrode; and one or more connection conductor lines formed on an outer surface of the capacitor body and connecting the first outer electrode to the third outer electrode or connecting the second outer electrode to the fourth outer electrode.

In a capacitor body of a multilayer capacitor, one second capacitor portion is sandwiched between two first capacitor portions. An ESR is controlled by setting a width of lead portions of third and fourth internal electrodes disposed in the second capacitor portion to be less than that of lead portions of first and second internal electrodes disposed in the first capacitor portions and by changing ratios between the first and second capacitor portions in the width of the lead portions and in the number of stacked internal electrodes. In the first capacitor portions, current paths from the internal electrodes to an external terminal electrode are widely distributed so that the first capacitor portions have a relatively low ESL, and accordingly, the ESL of the entire multilayer capacitor is reduced.

A multilayer capacitor comprised of dielectric layers stacked to form a device body in which a plurality of first internal electrode layers and a plurality of second internal electrode layers formed in planar shapes are alternately arranged while being separated through the dielectric layers, wherein the first external electrodes and second external electrodes are arranged at only a first end face of the device body, lead use columnar electrodes connect the internal electrode layers stacked close to the first end face of the device body and external electrodes, interlayer connection use columnar electrodes connect the internal electrode layers stacked at the inside of the device body, and the interlayer connection use columnar electrodes have cross-sectional areas larger than the cross-sectional areas of the lead use columnar electrodes.

A feedthrough capacitor having a pair of first terminal electrodes and a second terminal electrode is mounted on a mounting surface of a substrate. The substrate is an insulating substrate internally having first and second conductor portions isolated from each other, and has a plurality of first via holes, a plurality of second via holes, a plurality of first land electrodes, and a second land electrode. The first via holes and the second via holes, when viewed from the mounting surface side, are arranged in a matrix pattern and alternately arranged in a row direction and in a column direction. The feedthrough capacitor, when viewed from the mounting surface side, is located between a pair of said first via holes adjacent to each other in a direction intersecting with the row direction and also adjacent to each other in a direction intersecting with the column direction. The pair of first terminal electrodes are connected to the respective first land electrodes corresponding to the pair of adjacent first via holes. The second terminal electrode is connected to the second land electrode.

Disclosed is a method of implementing controlled equivalent series resistance (ESR) having low equivalent series inductance (ESL) of a multi-layer chip capacitor which includes a plurality of internal electrodes each having first polarity or second polarity which is opposite to the first polarity, and dielectric layers each disposed between the internal electrodes of the first polarity and the second polarity, wherein the internal electrodes having the first polarity and the internal electrodes having the second polarity are alternated at least once to form one or more blocks being stacked.

A multi-layered circuit board includes a first insulating layer, a second insulating layer, and a sheet capacitor that is located between the first insulating layer and the second insulating layer. The sheet capacitor includes a pair of electrodes that sandwich a dielectric. Lead wirings continue to the electrodes, respectively. The lead wirings are disposed on an opposite side of the first or the second insulating layer with respect to the sheet capacitor to overlap the electrodes when viewed from a stacking direction of the multi-layered circuit board. Because the lead wirings are arranged to overlap the electrodes in the stacking direction of the multi-layered circuit board, an ESL of the sheet capacitor is maintained low.