Ultra-low parasitic ESD protection device

Abstract

The invention relates to an ultra-low parasitic ESD protection device. The device comprises a P type substrate; a field oxide layer is formed on the P type substrate and is a polysilicon layer; one end of the polysilicon layer is a P+injection region, the other end of the polysilicon layer is a N+injection region, the middle part of the polysilicon layer is an intrinsic region; and a plurality of contact holes are alternately formed on the P+injection region and the N+injection region. Therefore, the ultra-low parasitic ESD protection device has the characteristics of ultra-low parasitic capacitance and ultra-low parasitic resistance, and can ensure excellent releasing capacity.

Description

technical field [0001] The invention relates to a protection circuit of a semiconductor integrated chip, in particular to an ultra-low parasitic ESD protection device which utilizes polysilicon diodes to discharge charges without changing process conditions. Background technique [0002] Electrostatic Discharge (ESD) events of varying degrees will occur in the manufacturing process of the integrated circuit IC chip and in the final system application. Electrostatic discharge is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside to the inside when an integrated circuit is floating. The whole process takes about 100ns to 200ns. In addition, when the integrated circuit is discharged, an equivalent high voltage of hundreds or even thousands of volts will be generated, which will break down the gate oxide layer of the input stage in the integrated circuit. As the size of MOS transistors in integrated circuits becomes...

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Problems solved by technology

In the weak small signal detection system, the parasitic capacitance 13 will couple the noise from the substrate, and the parasitic resistance 14 will affect the impedance matching. In the high frequency and radio frequency electronic system, if the PAD 12 and the internal circuit input stage are not well Impedance matching may cause partial reflection or even total reflection of the input signal, so that the input signal cannot be sent to the internal system

[0005] Traditional ESD protection devices have their own advantages and disadvantages in their discharge capabilities, but they are all connected to the substrate. The resulting parasitic capacitance will inevitably couple the substrate noise to the internal chip, and the formed parasitic resistance will affect the circuit at high frequencies. Impedance matching characteristics of

Although some people have done research on the traditional ESD device protection model, it is called substrate resistance engineering, but because the parameter extraction of substrate resistance has not been solved so far, it cannot be accurately provided to circuit designers, so I want to use traditional ESD protection devices To protect IC chips (especially high-frequency chips), the effect is not good

If noise and impedance matching problems are serious, even the design's excellent chip performance can be greatly affected

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