Pattern transferring method

Abstract

The invention provides a pattern transferring method, which comprises the following steps: providing a semiconductor substrate with a plurality of mask layers, wherein the mask layers which are furthest from the semiconductor substrate and are not etched are provided with photoresist layers, and the photoresist layers contain a photographic acidifier and alkyl phenoxy benzoic acid resin; exposing an objective pattern to the photoresist layer to form a photoresist layer with a semiconductor device pattern, wherein the depth of the semiconductor device pattern on the photoresist layer is less than the depth of the photoresist layer; performing silanization treatment on the surface of the photoresist layer with the objective pattern; forming an anti-plasma etching layer with an objective pattern shape on the photoresist layer; taking the anti-plasma etching layer on the photoresist layer as a mask; performing plasma etching on the photoresist layer until a mask layer is exposed; and taking the anti-plasma etching layer or the photoresist layer as the mask to etch the mask layer. The pattern transferring method does not need to coat an anti-reflection layer on the etched surface and avoids the unsmooth coating of the anti-reflection layer, thereby avoiding an unstable structure of pattern lines formed by the photoresist layer.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a pattern transfer method. Background technique [0002] In order to improve integration and reduce manufacturing costs, the critical dimensions of semiconductor devices are continuously reduced, and the number of semiconductor devices per unit area of ​​a chip is continuously increasing. While the critical dimensions of semiconductor devices are reduced, the patterns of semiconductor devices are also continuously miniaturized. However, the formation of fine patterns and fine pitches is becoming more and more difficult. In order to form fine patterns, a double exposure process for the pattern on the photomask is introduced on the film layer. [0003] The August 2007 issue of "Semiconductor Manufacturing" published an article "Prospects for the Application of Overlay Pattern Immersion Lithography Technology in 32nm Half-Pitch" which discloses the existing method of manufac...

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Problems solved by technology

[0008] When the above-mentioned prior art forms the second anti-reflection layer 107 by spin coating on the first anti-reflection layer 104a having the first semiconductor device pattern and the first mask layer 102, since the first anti-reflection layer having the first semiconductor device pattern 104a is covered with the second mask layer 103a having the first semiconductor device pattern, so that when the second anti-reflection layer 107 is coated, the second anti-reflection layer 107 is covered with the second mask layer 103a having the first semiconductor device pattern The groove 106 cannot be coated evenly and evenly. Therefore, when the second photoresist layer is exposed, the light energy received by the photoresist due to the unevenness of the second anti-reflection layer 107 is inconsistent, and the photoresist is easy to be exposed. The formed graphic structure is unstable and collapses

[0009] In addition, the second anti-reflection layer 107 tends to produce a standing wave effect during exposure, so that the sidewall of the photoresist pattern structure formed after exposure has poor steepness, which is not conducive to the etching process.

[0010] In addition, the prior art uses wet etching, and due to the anisotropy of the first mask layer 102 and the second mask layer 103, wet etching results in formation of T-shaped, inverted T-shaped, triangular, inverted triangular, trapezoidal, inverted trapezoidal, semi-dome or no-top phenomenon in the cross-section of the line, or the sidewall of the formed line is not perpendicular to the surface of the semiconductor substrate

Wet etching also tends to cause collapse of the lines formed on the first mask layer and the second mask layer

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