83results about How to "Minimize period" patented technology

Sensors (10, 110, 210, 310, 410) and a method for detecting an analyte are described. Sensors (10, 110, 210, 310, 410) each have a volume of a hydrophilic medium (24) that retains an amount of analyte proportionate to the concentration of analyte in a biological fluid, electrodes (12) and a redox enzyme in contact with medium (24), and an electron transfer mediator. The fluid contacts sensors (10, 110, 210, 310, 410) and at initially predetermined intervals intermittently applies a potential to electrode (12) sufficient to oxidize the mediator and sensing current through electrode (12) as a function of the duration of the applied potential. The applied mediator oxidizing applied potential is maintained for a period of time sufficient to determine the rate of change of current with time through electrode (12). The current flow is correlated with the current flow for known concentrations of the analyte in medium (24).

Apparatus, system, and methods for utilizing one or more computing devices to stage the movement of teeth during an alignment treatment are disclosed. The computing device receives an electronic representation of the patient's teeth in their initial position and an electronic representation of the teeth a final position for each tooth. A route each tooth will travel to reach its final position is determined, and the teeth are scheduled to move according to a movement pattern. Moreover, the schedule of movement takes into account a maximum rate of tooth movement for each tooth, the path of movement for each tooth, the distance each tooth needs to move, any needed tooth staggering, any needed round-tripping or tooth movement slowing. The invention also includes techniques for determining an optimum number of stages for the treatment based on the schedule of movement.

Mechanisms for providing hardware based dynamic load balancing of message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.

There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

A method of handover in a wireless communication system in which an asynchronous system and a synchronous system are mixed is disclosed. The method comprises the steps of: the asynchronous system ordering a dual mode mobile terminal to perform a handover from the asynchronous system to the synchronous system; when the handover order is received at the mobile terminal, the mobile terminal transmitting a frame or a preamble through a reverse traffic channel to the synchronous system, reporting to the synchronous system that the handover is completed and initiating a timer of the mobile terminal which is set according to a predetermined time; the mobile terminal switching from an asynchronous vocoder into a synchronous vocoder when the timer expires; and the wireless communication system switching vocoders of asynchronous and synchronous MSCs when the report is received.

Mechanisms for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing work loads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI Load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.

Circuits, systems, methods and software for controlling a power conversion and / or correcting and / or controlling a power factor in such conversion(s). The present invention generally takes a computational approach to reducing or minimizing zero current periods in the critical mode of power converter operation, and advantageously reduces zero current periods in the critical mode of power converter operation, thereby maximizing the power factor of the power converter in the critical mode and reducing noise that may be injected back into AC power lines. The present power factor controller allows for greater design flexibility, reduced design complexity, and reduced resolution and greater tolerance for error in certain parameter measurements useful in power factor correction and / or control.

Methods, apparatus and computer programs have been provided for mitigating a problem of non-optimal recovery from storage device failures. A method involves determining a required write performance for rebuilding data of a failed device, based at least partly on the potential read performance of storage devices in a data rebuild; and allocating a virtual storage area within available storage, which allocation of virtual storage is based at least partly on the required write performance. Data is rebuilt by writing to the allocated virtual storage area, and data recovery is completed by migrating this rebuilt data to at least one data storage device such as a spare physical storage device within the array.

Mechanisms are provided for performing setup operations for receiving a different amount of data while processors are performing message passing interface (MPI) tasks. Mechanisms for adjusting the balance of processing workloads of the processors are provided so us to minimize wait periods for waiting for all of the processors to call a synchronization operation. An MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, setup operations may be performed while processors are performing MPI tasks to prepare for receiving different sized portions of data in a subsequent computation cycle based on the history.

Mechanisms are provided for providing hardware based dynamic load balancing of message passing interface (MPI) tasks by modifying tasks. Mechanisms for adjusting the balance of processing workloads of the processors executing tasks of an MPI job are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. Thus, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.