31 results about "Single parity check" patented technology

A method and apparatus perform forward error correction in a wireless communication device in a wireless communication network. Application layer forward error correction (AL-FEC) capability information is transmitted during a capabilities exchange. A set of source packets are reshaped to k equal-sized source symbols. Systematic packets for the source symbols and at least one parity packet is encoded using a single parity check (SPC) AL-FEC code on the k source symbols. A header of each encoded packet includes a parity packet indicator. The encoded packets are processed in a media access control (MAC) layer and a physical (PHY) layer for transmission.

A communication channel including Reed-Solomon (RS) and single-parity-check (SPC) encoding/decoding. Multiple RS codewords are combined and then SPC encoded into an RS/SPC array. A soft-input soft-output (SISO) channel detector detects the RS/SPC encoded bits and provides soft (reliability) information on these bits. A combined RS and SPC error correction block provides a recovered user output. An iterative soft input decoding algorithm combines RS and SPC error correction.

The invention discloses a coding method for multi-dimensional crossing parallel cascade single-parity check code comprising that input information bit frame is separately passed through M interweavers and serial to parallel conversion then enters into crossover; output of crossover generates parity check bit frame P by passing P single-parity check encoder; U and P constitutes code word C; encoder computes code word C channel prior information according to receiving signal; U channel prior information is separately interweaved by M interweavers to get M channel prior information of interweaved information bit frame and first generation iteration coding; encoder executes iteration coding and simultaneously executes local coding, then gets outer information of M interweaved information bit frame, and computing prior information of next iteration; judging logarithm likelihood ratio information for U, obtaining coding result. The invention has merits of simple encoding and coding, low error floor and is used for correcting error of receiving signal.

The invention belongs to the fields of digital communication and digital storage and in particular relates to a multi-rate code encoding method for grouped Markov superposition coding based on time division. The method is used for encoding a binary information sequence u- with the length K being equal to (n-2)kBL into code words c- with the length N being equal to (n-2)nB(L+m<k>), wherein n is more than 2, k refers to a range of {1, 2,..., n-1}, namely a code rate set refers to {1/n, 2/n,..., (n-1)/n}, L is the number of (n-2)kB sequenced packets of equal length, m<k> is the memory length of subcodes with the code rate of k/n, and the memory length of an encoder is as shown in the specification. The method comprises the following steps: dividing the information sequence u- into L packets of equal length which are as shown in the specification, wherein t is equal to -1, -2,..., -(m<k>-1), -m<k>, and initializing a sequence v-(t) with the length of (n-2)nB; dividing a sequence which is as shown in the specification with the length of (n-2)kB into B packets at the moment t being equal to 0, 1,..., L-1 for performing time division encoding on [n, 1] repetition codes and [n, n-1] single parity check codes, thereby obtaining an encoding sequence which is as shown in the specification with the length of (n-2)nB; and calculating the t-th subsequence of the code words c- by combining the sequence as shown in the specification. The multi-rate codes based on time division provided by the invention are simple in design, wide in code rate range, low in decoding complexity and excellent in performance.

A method for encoding includes encoding K blocks of information for transmission on N subchannels responsive to a number of redundant blocks M according to one of i) employing a single parity check code when the number of redundant blocks M is about 1; ii) employing a code exhibited by a code graph having one third of variable nodes are connected to one of the check nodes, another one third of variable nodes is connected to the other check node and the remaining one third of variable nodes is connected to both check nodes, when the number of redundant blocks M is 2; iii) employing a first process for determining a code for the K blocks of information, when the number of redundant blocks M is about 3 together with K blocks of information less than about 150 or the number of redundant blocks M is about 4 together with K blocks of information less than about 20; and iv) employing a second process for determining a code for the K blocks of information with redundant block M values other than for steps i), ii) and iii).

This invention provides an iterative PCZZ data decoder that includes circuitry for utilizing all extrinsic information during iterative decoding by updating likelihood information for parity bits L_Pi, i=1, . . . , M during iterations. The extrinsic information for the parity bits is included in iterations by re-calculating soft values for parity bits L_Pi^(k) for each iteration k. In one embodiment the parity bit soft values are re-calculated in a plurality of circuit blocks following Max-Log-APP (MLA) decoder blocks, based on soft values for data bits L_Di^(k). In another embodiment the parity bit soft values are re-calculated recursively within the plurality of MLA decoders. The decoder operates to control the convergence of the decoder by monitoring a soft value of one parity check symbol, e.g., L^(k−1)[p(IM)], where p(IM) represents the last parity check bit in an I×M parity check array. A decoder iteration stopping rule may be implemented by testing a likelihood measure associated with a last parity check symbol in a parity check column. In one case the likelihood measure may be given by L^(k−1)[p(IM]>threshold, and in another case the likelihood measure may be given by L^(k−1)[p(I)]>threshold. The likelihood measure is given in general by: L^(k−1)[p(I)]>threshold, L^(k−1)[p(2I)]>threshold, . . . , L^(k−1)[p(IM)]>threshold, where the value of the threshold is a function of data block size.

The invention discloses a polar code fast serial cancellation list decoding algorithm based on bit flipping. According to the algorithm, the decoding rate is increased by adding identification of fourspecial nodes; meanwhile, a critical set is constructed, error propagation caused by previous decoding errors is avoided; a turnover position is judged and determined by respectively calculating loglikelihood ratio (LLR) values of two special nodes, namely an information bit R1 node and a single parity check (SPC) node; when the parity check bit does not meet the requirement, only the information bit corresponding to the most unreliable input LLR needs to be overturned, so that the overturning frequency is reduced, and the complexity is reduced. Simulation results show that when the block error rate is 10 <-5 >, the signal-to-noise ratio of the improved fast SCL decoding algorithm based on bit flipping is improved by 0.09 dB compared with that of an original SCL decoding algorithm basedon bit flipping, so that the improved decoding algorithm provides a reference algorithm under the condition of medium and short code lengths.

A method for encoding a quasi-cyclic low-density parity-check (LDPC) code according to an embodiment of the present invention comprises: a step of generating a multi-edge LDPC code matrix which comprises a high rate code matrix and a single parity check code matrix; and a step of encoding a signal using the multi-edge LDPC code matrix, wherein the single parity check code matrix may be configured by connecting a first matrix which is configured as a quasi row-orthogonal structure matrix and a second matrix which is configured as a pure row-orthogonal structure.

Disclosed are an apparatus and a method for LDPC encoding suitable for highly reliable and low latency communication. The disclosed apparatus comprises: a second inner encoding module for outputting parity bits by means of single parity calculations and accumulation device calculations using bit strings outputted from a first inner encoding module; and the first inner encoding module for outputting a part of the parity bits by means of single parity check calculations for the bits output from a second outer module, and for outputting rest of the parity bit strings by means of single parity check calculations and accumulation device calculations, with a part of the parity bits output by the second inner encoding module as an additional input.