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58results about How to "Increase array density" patented technology

Devices and methods for enrichment and alteration of circulating tumor cells and other particles

The invention features devices and methods for detecting, enriching, and analyzing circulating tumor cells and other particles. The invention further features methods of diagnosing a condition, e.g., cancer, in a subject by analyzing a cellular sample from the subject.
Owner:CELLECTIVE DX CORP +2

Device and method for detecting a substance of a liquid

ActiveUS7468608B2Eliminates high-frequency lossEliminates interfering inductanceAnalysing fluids using sonic/ultrasonic/infrasonic wavesShaking/oscillating/vibrating mixersResonancePiezo electric
A device for detecting at least one substance of a fluid includes at least one piezo-acoustic resonator with at least one piezo layer, an electrode arranged on the piezo-electric layer, at least one other electrode arranged on the piezo-electric layer and a surface section used for sorption of the substance of the fluid. The piezo-electric layer, the electrodes and the surface section are disposed in such a way that electric control of the electrodes leads to an oscillation of the resonator at a resonance frequency which depends upon the amount of the substance which is sorbed on the surface section. The thickness of the pioelectric layer is in the region of 0.5 to 20 μm and the resonance frequency of the oscillation ranges from 500 MHz to 2 GHz. The device is a mass sensor with a piezo-acoustic high-frequency thin film resonator.
Owner:BIOMENSIO LTD

NAND string wordline delay reduction

An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line selection delay by driving the adjacent word lines to a higher initial voltage and then reducing it to the final target voltage. As the capacitive coupling in between the NAND word lines is a larger effect when the voltages are being lowered, this has the effect of damping out the voltage initially induced in the lower voltage word line by the rising voltages on the adjacent word lines, reducing the overall selection time.
Owner:MICRON TECH INC

Embedded EEPROM array techniques for higher density

An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.
Owner:TEXAS INSTR INC

Embedded EEPROM array techniques for higher density

An array structure of single-level poly NMOS EEPROM memory cells and method of operating the array is discussed implemented in a higher density embedded EEPROM layout that eliminates the use of high voltage transistors from the array core region. If they are utilized, the high voltage transistors are moved to row and column drivers in the periphery region to increase array density with little or no added process complexity to allow economic implementation of larger embedded SLP EEPROM arrays. During program or erase operations of the array, the method provides a programming voltage for the selected memory cells of the array, and a half-write (e.g., mid-level) voltage to the remaining unselected memory cells to avoid disturbing the unselected memory cells of the array.
Owner:TEXAS INSTR INC

Nand string wordline delay reduction

An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line selection delay by driving the adjacent word lines to a higher initial voltage and then reducing it to the final target voltage. As the capacitive coupling in between the NAND word lines is a larger effect when the voltages are being lowered, this has the effect of damping out the voltage initially induced in the lower voltage word line by the rising voltages on the adjacent word lines, reducing the overall selection time.
Owner:MICRON TECH INC

Scanning kelvinmicroprobe system and process for biomolecule microassay

There is provided a system and process for detecting biomolecular interaction on a substrate having a biomolecule immobilized on a surface of the substrate. The system and process incorporate a scanning Kelvin microprobe (SKM) capable of analyzing surface topography as well as a contact potential difference image signal. Also provided is the use of SKM in measuring and analyzing biochemical molecular interactions between a probe bound to the surface of the substrate, and a target suspected to be present in a liquid sample. One of the probe and target combination is a biomolecule such as a nucleic acid, a polypeptide, or a small molecule, and an antibody antigen combination may be used.
Owner:SENSORCHEM INT

Gate coupling in floating-gate memory cells

Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.
Owner:MICRON TECH INC

Optoacoustic/ultrasonic dual mode endoscope based on miniature piezoelectric ultrasonic transducer arrays

The invention discloses an optoacoustic / ultrasonic dual mode endoscope based on piezoelectric micromachined ultrasonic transducer arrays. The optoacoustic / ultrasonic dual mode endoscope includes a piezoelectric micromachined ultrasonic transducer (PMUT) array probe (2), a PMUT array element (1), an integrated circuit (3), a plane lens (4), a condenser lens (6), an optical fiber coupling collimator (7), a single-mode fiber (8), an optical fiber FC / APC connector (9), an optical fiber (10), a signal line (11) and an housing (12). The optoacoustic / ultrasonic dual mode endoscope is characterized in that, the piezoelectric micromachined ultrasonic transducers are adopted, the transducers and the integrated circuit are good in compatibility during manufacturing process, and the transducers are easy to form an array; transducer arrays are adopted, the endoscope does not need to rotate, the imaging speed is raised, real time imaging is achieved; and the multiple transducer arrays can effectively raise the signal to noise ratio of a signal, deep imaging through focusing and scanning is achieved. The optoacousitc / ultrasonic dual mode endoscope can be widely applied to fields of medical endoscopes and industrial flaw detection, and particularly has great application value in in-vivo scar tissue identification, assessment of damage of ablation of tissue, atherosclerotic degree assessment and the like.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA

Static source plane in stram

The present disclosure relates to a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A transistor is electrically between the magnetic tunnel junction cell and the source line. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.
Owner:EVERSPIN TECHNOLOGIES

Dynamic random access memory device with the combined open/folded bit-line pair arrangement

A dynamic random access memory device includes a semiconductor substrate, a plurality of parallel word lines on the substrate, and a plurality of pairs of bit lines transverse to the word lines on the substrate. An array of one-transistor memory cells are selectively arranged at the cross points as defined between the word lines and the bit lines. The array is subdivided into a plurality of subarray sections. A sense amplifier section is connected to the bit lines. The sense amplifier section includes first and second sense amplifier circuits. Adjacent bit-line pairs of the bit lines include a first bit-line pair and a second bit-line pair, one of which has a folded bit-line arrangement being included in a certain subarray section to be connected to the first sense amplifier circuit, and the other of which has an open bit-line arrangement that extends into the subarray section and another subarray section adjacent thereto, and is connected to the second sense amplifier circuit.
Owner:KK TOSHIBA

Dense semiconductor fuse array

The present invention provides a dense semiconductor fuse array having common cathodes. The dense semiconductor fuse array of the present invention occupies less area than conventional semiconductor fuse arrays, can comprise integrated diodic components, and can require only one metal wiring layer for making electrical connections to the fuse array.
Owner:GLOBALFOUNDRIES US INC

Gate coupling in floating-gate memory cells

Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.
Owner:MICRON TECH INC

Method for constructing micro-nano structure with antibacterial function on surface of metal substrate

The invention discloses a method for constructing a micro-nano structure with an antibacterial function on the surface of a metal substrate. The method comprises the following steps: carrying out technologies of metal surface cleaning, annealing heat treatment, lifting and drawing to prepare a ZnO seed crystal layer and hydrothermal growth of a nano array for surface treatment, and finally obtaining a metal plate target product with a ZnO nano array. The ZnO array prepared by the method has a large number of nanoscale tip array structures, the array density can reach 1*10 <7>-1*10 <9> pieces / cm <2>, and the tip diameter of nanorods forming the array ranges from 30 nm to 150 nm. The surface of the array can rapidly sterilize bacteria by making contact with bacterial strains, the surface bacteria can be killed within 1 minute, the sterilizing rate for the escherichia coli (ATCC 25922) and the staphylococcus aureus (ATCC 6538) can reach more than 99.99%, and the surface of the array has a rapid broad-spectrum bactericidal performance.
Owner:SOUTHWEST JIAOTONG UNIV

Method of manufacturing semiconductor device

A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.
Owner:SHANGHAI HUAHONG GRACE SEMICON MFG CORP

Solar cell package type with surface mount technology structure

A solar cell package type with surface mount technology structure, comprising: a solar cell having a first electric terminal at the bottom thereof and a second electric terminal at the top thereof; at least a connection electric terminal capped at both sides of the solar cell in such a way that the top of the connection electric terminal is connected to the second electric terminal; and at least an insulation layer capped at both sides and partially placed at the bottom of the solar cell in such a way that it is interposed between the electric terminal and the solar cell for avoiding the short current and the water penetration. In this way, this package in accordance with the invention tends to increase the array density of the solar cells on the substrate and to minimize the manufacturing cost.
Owner:CHUANG YUNG HUI +1

Scanning kelvin microprobe system and process for biomolecule microassay

There is provided a system and process for detecting biomolecular interaction on a substrate having a biomolecule immobilized on a surface of the substrate. The system and process incorporate a scanning Kelvin microprobe (SKM) capable of analyzing surface topography as well as a contact potential difference image signal. Also provided is the use of SKM in measuring and analyzing biochemical molecular interactions between a probe bound to the surface of the substrate, and a target suspected to be present in a liquid sample. One of the probe and target combination is a biomolecule such as a nucleic acid, a polypeptide, or a small molecule, and an antibody antigen combination may be used.
Owner:THOMPSON MICHAEL +2
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