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Inclined silicon groove etching process

A dipped silicon technology, which is applied in the manufacture of electrical components, semiconductor/solid-state devices, circuits, etc., can solve the problems of inability to meet the isolation requirements of bipolar integrated circuits, affect the performance and reliability of three-dimensional integrated devices, and increase leakage, and achieve Optimizing the morphology of silicon grooves, eliminating voids, and improving the breakdown voltage

Active Publication Date: 2019-02-12
西安西岳电子技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The morphology of the traditional silicon groove etching process is steep, see figure 1 , voids will be formed during the subsequent filling process, see figure 2 , resulting in increased leakage and reduced withstand voltage, which affects the performance and reliability of three-dimensional integrated devices, and cannot meet the isolation requirements in bipolar integrated circuits

Method used

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  • Inclined silicon groove etching process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0044] Step 1: grow a 13 μm epitaxial layer on the surface of p-100 type SOI substrate, and then grow 1 μm SiO in the furnace tube 2 , using SiO 2 As a hard mask layer 2 for silicon trench etching, the SiO 2 The surface is coated with photoresist to form a photoresist layer 1, exposed and developed to expose the SiO that needs to be etched 2 Window, the window pattern is a groove, the groove width is 0.8μm;

[0045]Step 2: Use CENTURA5200 silicon dioxide plasma dry etching machine; wherein, the chamber pressure is 200mT, the electrode power is 600W, and the process gas includes CHF with a flow rate of 30sccm 3 , CF with a flow rate of 30sccm 4 and Ar at a flow rate of 150 sccm, etch all the way to the wafer surface.

[0046] After 240s, the etching of the hard mask is completed.

[0047] Step 3: Use CENTURA5202 dry etching machine for silicon etching, that is, deep silicon groove etching. Set the silicon groove etching bias power to 50W, the frequency to 120Hz, the bias ...

Embodiment 2

[0052] Step 1: grow a 13 μm epitaxial layer on the surface of p-100 type SOI substrate, and then grow 1 μm SiO in the furnace tube 2 , using SiO 2 As a hard mask layer 2 for silicon trench etching, the SiO 2 The surface is coated with photoresist to form a photoresist layer 1, exposed and developed to expose the SiO that needs to be etched 2 Window, the window pattern is a groove, the groove width is 1.0μm;

[0053] Step 2: Use CENTURA5200 silicon dioxide plasma dry etching machine; wherein, the chamber pressure is 200mT, the electrode power is 600W, and the process gas includes CHF with a flow rate of 30sccm 3 , CF with a flow rate of 30sccm 4 and Ar at a flow rate of 150 sccm, etch all the way to the wafer surface.

[0054] After 240s, the etching of the hard mask is completed.

[0055] Step 3: Use CENTURA5202 dry etching machine for silicon etching, that is, deep silicon groove etching. Set the silicon groove etching bias power to 55W, the bias power frequency to 110H...

Embodiment 3

[0060] Step 1: grow a 13 μm epitaxial layer on the surface of p-100 type SOI substrate, and then grow 1 μm SiO in the furnace tube 2 , using SiO 2 As a hard mask layer 2 for silicon trench etching, the SiO 2 The surface is coated with photoresist to form a photoresist layer 1, exposed and developed to expose the SiO that needs to be etched 2 Window, the window pattern is a groove, the groove width is 1.4μm;

[0061] Step 2: Use CENTURA5200 silicon dioxide plasma dry etching machine; wherein, the chamber pressure is 200mT, the electrode power is 600W, and the process gas includes CHF with a flow rate of 30sccm 3 , CF with a flow rate of 30sccm 4 and Ar at a flow rate of 150 sccm, etch all the way to the wafer surface.

[0062] After 240s, the etching of the hard mask is completed.

[0063] Step 3: Use CENTURA5202 dry etching machine for silicon etching, that is, deep silicon groove etching. Set the silicon groove etching bias power to 52W, the bias power frequency to 130H...

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Abstract

The invention discloses an inclined silicon groove etching process. The process includes steps: forming a hard mask layer on the surface of a to-be-etched wafer, coating the surface of the hard mask layer with photoresist, and performing exposure and development to expose a to-be-etched hard mask layer window; performing hard mask etching at the exposed window, and etching to the surface of the wafer; performing silicon groove etching at the window subjected to hard mask etching, and etching to a set value of silicon groove depth, wherein etching gas is SF6, passivation gas comprises O2 and Hbr, bias power is 50-55W, bias power efficiency is 110-130Hz, bias power cycle is 65%-75%, and source radio-frequency power is 1000-1100W; removing photoresist in a non-silicon-groove area according toa dry-process photoresist removal method. A silicon groove side wall angle is optimized from 90 degrees to be close to 80 degrees; in a subsequent silicon groove filling process, voids formed after filling are eliminated, and accordingly breakdown voltage is increased, electric leakage is reduced, and reliability of a dielectric isolation integrated process is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, and relates to a dipped silicon groove etching process. Background technique [0002] In integrated circuit technology, deep silicon grooves are mainly used for isolation in bipolar integrated circuits and capacitor production in DRAM. Due to the large operating current in bipolar integrated circuits, deep silicon groove isolation technology is the most important for bipolar integrated circuits. It is very important, and it can also reduce the device area. For DRAM production, deep silicon trenches can prepare large capacitors and occupy a small area. In deep trench isolation and deep trench capacitance, the etching technology of deep silicon trenches is very critical. Currently, the commonly used deep silicon groove fabrication technology mainly adopts hard mask ICP etching technology to realize the deep silicon groove fabrication. The morphology of the traditional silicon ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/3065H01L21/762
CPCH01L21/3065H01L21/76224
Inventor 郝军李林代鹏昊何鑫鑫陈宝忠
Owner 西安西岳电子技术有限公司
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