40results about How to "Increase in inhibition area" patented technology

A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

An electro-optical device includes a substrate, a first terminal that is formed on the substrate, a second terminal that is formed on the substrate and arranged in a first direction with respect to the first terminal, a third terminal that is formed on the substrate, and arranged in a second direction different from the first direction with respect to the first terminal, and of which the position in the first direction is the same as the first terminal, and a wiring that is formed on the substrate and connected to the third terminal.

A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

A solid-state image pickup apparatus 1A is formed such that M×N (where M<N and M and N are integers greater than or equal to 2) pixels are two-dimensionally arrayed in M rows and N columns, and has a photodetecting section 10A having a rectangular photosensitive surface whose longitudinal direction is the row direction. The solid-state image pickup apparatus 1A is supported rotatably by a rotation controlling section, and the rotation controlling section controls a rotation angle of the solid-state image pickup apparatus 1A such that the longitudinal direction of the photodetecting section 10A is made parallel to a moving direction B of the solid-state image pickup apparatus 1A in one imaging mode of the two imaging modes, and the longitudinal direction of the photodetecting section 10A is made perpendicular to the moving direction B of the solid-state image pickup apparatus 1A in the other imaging mode of the two imaging modes.

A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.

The present invention provides a display panel including: a first input terminal group in which input terminals are disposed at intervals along first long side of a rectangular driver IC facing a panel end portion; a second input terminal group in which input terminals are disposed at intervals along the second long side of the driver IC facing a display section; a first wiring group connected to the first input terminal group, that extends under the first short side of the driver IC and extends out from between the driver IC and the panel body; and a second wiring group connected to the second input terminal group, that passes under the second long side of the driver IC and extends out from between the driver IC and the panel body.

A solid-state image pickup apparatus 1A is formed such that M×N (where M<N and M and N are integers greater than or equal to 2) pixels are two-dimensionally arrayed in M rows and N columns, and has a photodetecting section 10A having a rectangular photosensitive surface whose longitudinal direction is the row direction. The solid-state image pickup apparatus 1A is supported rotatably by a rotation controlling section, and the rotation controlling section controls a rotation angle of the solid-state image pickup apparatus 1A such that the longitudinal direction of the photodetecting section 10A is made parallel to a moving direction B of the solid-state image pickup apparatus 1A in one imaging mode of the two imaging modes, and the longitudinal direction of the photodetecting section 10A is made perpendicular to the moving direction B of the solid-state image pickup apparatus 1A in the other imaging mode of the two imaging modes.

The solid-state image pick-up device (1) includes a photodetecting section (10) which is formed by two-dimensionally aligning M×N (M and N are integers not less than 2) pixels in M rows and N columns and has a rectangular photodetecting surface. This solid-state image pick-up device (1) is supported rotatably by a rotation controlling section, and the rotation controlling section controls the rotation angle of the solid-state image pick-up device (1) so that the row direction or column direction of the photodetecting section (10) becomes parallel to the movement direction (B) of the solid-state image pick-up device (1) in one of the two imaging modes, and both of the row direction and the column direction of the photodetecting section (10) tilt with respect to the movement direction (B) of the solid-state image pick-up device (1) in the other imaging mode of the two imaging modes.

A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.

A semiconductor circuit apparatus includes a booster which is connected to a single power supply and outputs a power supply voltage of the power supply or a voltage different from the power supply voltage, and a boost controller which controls whether to output the power supply voltage of the power supply or the voltage different from the power supply voltage.

An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.

Image data is separated from three lines of image data in accordance with a storage capacity of a source memory. The separated image data is transferred to the source memory, Several pieces of image data are read out in sequence from the transferred image data and forwarded to a filtering process. These operations are then repeated to provide a line of filtered image data.

The present invention provides a display panel including: a first input terminal group in which input terminals are disposed at intervals along first long side of a rectangular driver IC facing a panel end portion; a second input terminal group in which input terminals are disposed at intervals along the second long side of the driver IC facing a display section; a first wiring group connected to the first input terminal group, that extends under the first short side of the driver IC and extends out from between the driver IC and the panel body; and a second wiring group connected to the second input terminal group, that passes under the second long side of the driver IC and extends out from between the driver IC and the panel body.

A semiconductor circuit apparatus includes a booster which is connected to a single power supply and outputs a power supply voltage of the power supply or a voltage different from the power supply voltage, and a boost controller which controls whether to output the power supply voltage of the power supply or the voltage different from the power supply voltage.

A semiconductor device which is provided to correspond to each of a plurality of nozzles discharging a liquid and controls a plurality of drive elements causing a liquid to be discharged from each nozzle by an application of a drive signal includes a detection circuit which detects a residual vibration signal of the drive element, an output terminal which is provided to correspond to each of the plurality of drive elements, a discharge transistor which controls an application of the drive signal to the drive element through the output terminal, and a detection transistor which controls an application of the residual vibration signal to the detection circuit through the output terminal, in which the detection transistor is smaller than the discharge transistor in size, and the discharge transistor is disposed between the detection transistor and the output terminal.

An electro-optical device includes a substrate, a first terminal that is formed on the substrate, a second terminal that is formed on the substrate and arranged in a first direction with respect to the first terminal, a third terminal that is formed on the substrate, and arranged in a second direction different from the first direction with respect to the first terminal, and of which the position in the first direction is the same as the first terminal, and a wiring that is formed on the substrate and connected to the third terminal.

A semiconductor device includes: a first transistor having a control electrode coupled to an input node receiving a signal synchronized with a clock, a first conductive electrode coupled to an output node, and a second conductive electrode; a second transistor having a control electrode coupled to the input node, a first conductive electrode coupled to the output node, and a second conductive electrode coupled to a power supply node; and a first switch element connected between the power supply node and the second conductive electrode of the second transistor and turned on and off based on a first control signal indicating a detection result of a frequency of the clock.

An object is to provide a level shift circuit that operates stably. A semiconductor device includes a level shift circuit including first to fourth transistors and a buffer circuit. One of a source and a drain (S / D) of the first transistor is connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is connected to one of a source and a drain of the third transistor. A gate of the first transistor and a gate of the fourth transistor are connected to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor. A gate of the third transistor is connected to a wiring to which an input signal is input. An input terminal of the buffer circuit is connected to one of a source and a drain of the fourth transistor. An output terminal of the buffer circuit is connected to a gate of the second transistor and a wiring to which an output signal is output.