413 results about "Common source line" patented technology

A spin transfer torque memory device and a method for manufacturing the same. The spin transfer torque memory device comprises a MRAM cell using a MTJ and a vertical transistor. A common source line is formed in the bottom of the vertical transistor, thereby obtaining the high-integrated and simplified memory device.

A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines.

A non-volatile semiconductor memory device having a write mode in which wrong writing is prevented surely. The storage device comprises a NAND cell comprising a plurality of memory transistors connected in series and also connected at one end via a select gate transistor CG1 to a bit line BL and at the other end via a select gate transistor SG2 to a common source line SL. A write voltage Vpgm is applied to a control gate of a selected memory transistor in the NAND cell and Vss is applied to the controls gates of non-select memory transistors each adjacent to the selected memory transistor to thereby write data into the select memory transistor. When a second memory transistor from the bitline BL side is selected in the writing operation, a medium voltage Vpass is applied to the control gate of a first non-selected memory transistor from the bit line BL side, and a medium voltage Vpass is applied to the control gates of third and subsequent non-selected memory transistors from the bit line BL side.

A semiconductor memory device, comprising: a memory cell array of a plurality of memory cell units, each memory cell unit including a plurality of serially connected memory cells formed on the same well region, each memory cell having a floating gate and a control gate stacked, said serially connected memory cells having one end serially connected to a first selection gate transistor, said serially connected memory cells having the other end connected to a common source line via a second selection gate transistor; a sense amp connected to one end of said first selection gate transistor via a bit line and operative to read data out of said memory cell array; and wherein a voltage applied to said well region and said source line varies to cancel a change of threshold of said memory cells depending on the temperature.

A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.

NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.