41 results about "Advanced Programmable Interrupt Controller" patented technology

Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

An advanced programmable interrupt controller (APIC) identification (ID) configuration method is applied to a multiprocessor computer system. The method assigns a postponed ID to each CPU's APIC IDs respectively during the initialization. Plural reserved IDs are assigned to the I / O APICs. A multiprocessor configuration table in a basic input output system (BIOS) will be updated with renewed ID configuration, to avoid an ID conflict when processing the interrupt request from the peripheral devices and raise the stability of the multiprocessor computer system.

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input / output (MMIO).

Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input / output (MMIO).

A virtual machine monitor, a virtual machine system and a clock distribution method thereof. The clock distribution method includes: distributing real clock resource to a Guest Operation System (GOS), and saving correspondence between said GOS and said real clock resource; intercepting an access operation of said GOS to a virtual clock resource; sending said access operation to the corresponding real clock resource according to said correspondence, and then performing a write operation, or injecting an interrupt of said real clock resource into a local Advanced Programmable Interrupt Controllers (APIC) of a virtual CPU of the corresponding GOS of said GOSs.

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input / output (MMIO).

In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC / AT compatible. In a mobile Internet device (MID) General Purpose Input / Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed.

Certain embodiments of the present invention are directed to providing efficient and easily-applied mechanisms for inter-core and inter-processor communications and inter-core and inter-processor signaling within multi-core microprocessors and certain multi-processor systems. In one embodiment of the present invention, local advanced programmable interrupt controllers within, or associated with, cores of a multi-core microprocessor and / or processors of a multi-processor system are enhanced so that the local advanced programmable interrupt controllers can be configured to automatically generate inter-core and inter-processor interrupts when WRITE operations are directed to particular regions of shared memory.

The present invention discloses a virtual machine system and a visit processing method of an advanced programmable interruption controller. The method includes an address mapping procedure in which a virtual machine monitor sets up an APIC virtual register space and a table mapping of APIC initial address and adds the address mapping table to the table of a virtual machine client operating system; an APIC visit control procedure in which the client operating system carries out the visit by compulsorily involving in the virtual machine monitor when visiting the first type register of APIC, and conducts the direct visit according to the address mapping table when visiting the second type register of APIC. The operation of the first type register can result in the change of other registers of APIC and the operation of the second type register can not affect other registers of APIC. The present invention greatly shortens the visit cycle of APIC and simplifies the operation.

In some embodiments, the invention involves a dynamic interrupt route discovery method with local APIC (Advanced Programmable Interrupt Controller) retriggering to accommodate architectures that are not PC / AT compatible. In a low power mobile device, General Purpose Input / Output (GPIO) pins are dynamically allocated and IRQs are retriggered by a GPIO driver to multiplex the requests to an appropriate device. Other embodiments are described and claimed.

The invention provides an interrupt processing method, an IOAPIC (Input / Output Advanced Programmable Interrupt Controller) and a computer system, relates to the technical field of the computer and is used for the IOAPIC to accurately forward an interrupt request. According to a preset mapping relationship between an IOAPIC physical pin and a processor or a processor cluster, the IOAPIC forwards the interrupt request, and an IOAPIC interrupt forwarding error can be avoided to a certain degree. The interrupt processing method comprises the following steps of: the IOAPIC receives a first interrupt request sent from first peripheral equipment; according to a corresponding relationship, which is recorded by a management operating system, between each load operating system and the hardware resource of each load operating system, the first load operating system corresponding to the first peripheral equipment is determined; and according to the preset mapping relationship between the IOAPIC physical pin and the processor or the processor cluster, through the physical pin corresponding to the processor or the processor cluster of the first load operating system, the first interrupt request is sent to the processor or the processor cluster of the first load operating system.