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Preparation method of single-layer atomic channel fin type field effect transistor and product

A fin-type field effect and transistor technology, applied in the field of applied research, to achieve strong gate control ability, good ohmic contact, and rich selectivity

Active Publication Date: 2020-06-19
INST OF METAL RESEARCH - CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, how to achieve vertically independent two-dimensional nanosheets in the experiment is still very challenging.

Method used

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  • Preparation method of single-layer atomic channel fin type field effect transistor and product
  • Preparation method of single-layer atomic channel fin type field effect transistor and product
  • Preparation method of single-layer atomic channel fin type field effect transistor and product

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0062] (1) SOI substrate of 300 nanometer silicon on the top layer (structural schematic diagram as image 3 Shown in a) The surface was spin-coated with LOR-7A (3K rpm, heated at 190°C, 5 minutes) and PMMA950K A7 (5K rpm, heated at 190°C, 5 minutes), and then exposed by electron beam exposure technology, and developed with Solution 1 (IPA / DI Water=1 / 3) was developed for 1 minute, developer 2 (CD-26) was developed for 35 seconds, and dried with nitrogen. Then use electron beam evaporation to deposit 200 nm thick metal nickel as a protective layer, and use inductively coupled plasma etching to remove the SOI top layer silicon material without metal protection, and finally dissolve the metal nickel with hydrochloric acid to obtain a vertical step pattern. The schematic diagram of the structure is as follows image 3 As shown in b, the actual enlarged picture is shown in Figure 4 shown;

[0063] (2) Use the atomic layer deposition method to deposit a uniform and dense hafnium ...

Embodiment 2

[0072] The difference from Example 1 is: the SOI substrate described in step (1) can be replaced with other substrates, such as a substrate with a similar SOI type three-layer structure, or a double-layer structure substrate, wherein the top layer can be Semiconductor, metal or insulator, the underlying material is an insulator.

[0073] Finfield-effect transistors with single-atom-layer-thick channel materials can be obtained.

Embodiment 3

[0075] The difference from Example 1 lies in that the thickness of the SOI top layer silicon in step (1) is different.

[0076] FinFETs with single-atom-layer-thick channel materials are available at different heights (up to microns).

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Abstract

The invention discloses a fin type field effect transistor with a monoatomic layer thickness channel material and a preparation method thereof. The fin type field effect transistor takes a high dielectric constant material as a dielectric layer and takes a single-layer transition metal chalcogenide as a channel material. The preparation method comprises the following steps: firstly, etching a vertical step or a vertical array structure on a substrate; depositing and uniformly coating a dielectric layer on the side wall, synthesizing a single-layer transition metal chalcogenide at the step, obtaining a vertical monoatomic layer thickness channel material by adopting an anisotropic etching process, and finally obtaining the fin field effect transistor of the monoatomic layer thickness channel material by combining selective wet etching and micro-nano processing process, wherein the fin width of the obtained transistor is only 0.6 nm; the fin type field effect transistor with the height of hundreds of nanometers can be obtained based on different thicknesses of the top layer of the substrate; a high-density fin array type fin field effect transistor can be obtained by preparing the step array and is used for constructing a logic device with high integration and low power consumption.

Description

technical field [0001] The invention belongs to the applied research field of nano artificial compound, micro-nano device, logic device, etc., and specifically provides a method for preparing a fin field-effect transistor of a single-atom-layer-thick channel material. Background technique [0002] Moore's Law states that the number of transistors per unit area in an integrated circuit will double every year, which requires that the size of transistors be continuously reduced. When the channel width reaches below 10 nanometers, the quantum confinement effect of the traditional planar field effect transistor is significant, which hinders its further reduction in size. One of the solutions is to use a three-dimensional structure to construct a fin field effect transistor composed of a gate and a channel material covered by a dielectric layer. Thanks to the larger contact area between the gate and the channel material, and the thinner thickness of the channel material, the cont...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/10H01L29/24H01L29/423H01L29/78H01L21/04
CPCH01L29/1033H01L29/24H01L29/42312H01L29/66969H01L29/785
Inventor 韩拯陈茂林孙东明孙兴丹王汉文刘航董宝娟刘松
Owner INST OF METAL RESEARCH - CHINESE ACAD OF SCI
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