The invention discloses an NAND type ROM. A
column structure comprises a plurality of NAND type
memory cell series structures and bit lines. Each storage unit series structure is connected between thecorresponding
bit line and the corresponding source line; each
memory cell series structure in the row structure forms a corresponding
memory cell series structure row; the
source lines form a dynamic split type source
electrode bias
voltage structure, and specifically, any two adjacent storage unit series structures in the storage unit series structure row are connected with different
source lines;
source lines connected with different memory
cell series structures in the same column are different. The bias
voltage in the reading process is set as follows: the source line corresponding to the read memory
cell is connected with a low level, the source line corresponding to the memory
cell series structure adjacent to the read memory cell in the same row is connected with a high level, andthe source line corresponding to the memory cell series structure adjacent to the read memory cell in the same
column structure is connected with a high level. The reading
voltage drop caused by bitline electric leakage,
bit line capacitance sharing and
bit line crosstalk can be eliminated.