57 results about "Register window" patented technology

One embodiment of the present invention provides a system that dynamically allocates physical registers in a windowed processor architecture. The system includes a physical register file and a register map that maps architectural registers defined within an executing program to physical registers within the physical register file. The system also includes a window allocation mechanism that allocates a new name space for a register window without allocating physical registers for the register window, thereby allowing the physical registers to be dynamically allocated as needed instead of being allocated at window initialization time.

Security-state-reporting and data-control functionality introduced into a computer system to monitor and report the security state of the computer system and to store and make selectively available, for processes executing within a computer system, security-state-associated data. The hardware element includes two control registers, a current-security-state control register (“CSS”) and a current-data-bank control register (“CDB”). When the CSS is read, the CSS reports the current security state of the computer system, with security states represented as unsigned integers starting from a highest security level of 0 and decreasing with unsigned integers of increasing magnitudes. The CDB controls access to one or more data-register banks, positioning a data-register window to allow access only to those data-register-bank registers associated with the currently reported security state.

The present invention discloses Power control method in passive optical network, light sender of OLTPON terminal port transmits light signal with self maximum emission power at register windows to assure all ONU register success successfully; all ONU with establishing connection below the OLTPON terminal port can steadily receives light signal transmitted from the OLTPON terminal port by dynamic adjusting emission power of light sender of OLTPON terminal port in data-transmission windows. Adopting method of the present invention can dynamic regulate light signal emission power of OLT and ONU in PON system, thereby power loss of PON system is decreased.

In processor architectures that support allocation of register windows to called procedures, functions or methods, register windowing mechanisms can be used to facilitate suspension of a mutator thread (or mutator threads) while imposing negligible overhead on the mutator computation during periods when thread suspension is not requested. Reduced Instruction Set Computer-(RISC)-oriented processor architectures often employ register windows (typically partially-overlapped register windows) and can therefore benefit from the technique. Variations can be employed even in processors (RISC or otherwise) that do not employ register windowing as long as the processor (by itself or in cooperation with software) provides facilities for allocating and reclaiming resources in correspondence with calls to, and returns from, procedures, functions or methods. Mechanisms are provided to spill values from the fixed set of resources to a secondary store and to fill values from the secondary store into the fixed set in correspondence with function call triggered overflows and function return triggered underflows. In some configurations, modified spill and/or fill mechanism(s) are used to suspend threads at safe points coinciding with call and/or return sites. Because the modified spill and/or fill mechanism(s) impose negligible overhead when not employed and can be engaged in response to an event (e.g., a start garbage collection event), safe points can be defined at call and/or return points throughout mutator code to reduce the latency between the event and suspension of threads.

In the structure of register files composed of a master register file and a working register file, when data is read, the working register file is accessed. When data is written, the both the master register file and the working register file are accessed. In the working register file, data of the current window, and data preceded thereby, and data followed thereby are stored. Thus, even if the SAVE instruction or the RESTORE instruction are successively executed, instructions can be processed out of order. As a result, the efficiency of the process is improved.

In one embodiment, a processor is configured to execute a window swap instruction. The processor comprises a register file (that comprises a plurality of registers) and first and second execution units coupled to the register file. A first pipeline associated with the first execution unit has a first number of pipeline stages, and a second pipeline associated with the second execution unit has a second number of pipeline stages. The first execution unit is configured to change the current register window from the first register window to the second register window in the register file in response to the instruction. The second execution unit is configured to perform an operation defined by the instruction and write the result to the register file. The second number of pipeline stages exceeds the first number, whereby the second register window is established in the register file prior to writing the result.

The embodiment of the invention relates to the technical field of communications and discloses a method, system and device for adjusting a register window of a passive optical network (PON). The method comprises the following steps: sending pre-equalized delay adapting to a preset initial register window to an optical network unit (ONU) to be registered; receiving information fed back by the ONU to be registered in accordance with the pre-equalized delay, and carrying out range measurement on the ONU to be registered; according to a range measurement result, adjusting the pre-equalized delay and sending the adjusted pre-equalized delay to the ONU to be registered, or simultaneously adjusting the initial register window and the pre-equalized delay, and sending the adjusted pre-equalized delay to the ONU to be registered; and receiving registration information sent by the ONU to be registered in accordance with the adjusted pre-equalized delay, and carrying out interaction with the ONU to be registered so as to register the ONU to be registered. According to the embodiment of the invention, an ONU in the PON can be ensured to carry out normal communication with an optical line terminal (OLT).

A technique for handling window-fill and/or window-spill operations that improves the performance of a processor over traditional techniques is presented. The window-fill and window-spill operations can be handled in hardware using helper instructions (helpers) prior to the generation of a trap (exception). Fetched instructions are examined prior to forwarding for execution to detect a potential register window boundary condition necessitating, for example, a window-fill or window-spill operation. Vectors are generated for a helper storage within the processor to retrieve helpers for resolving the condition. The helpers are forwarded for execution prior to the instruction that would cause the condition. In some embodiments, to improve the processing, individual helper storages are implemented for every condition. The use of helpers to resolve a register window boundary condition eliminates the generation of a trap and the use of trap handler code.

A method and apparatus for handling window management instructions without post serialization in an out-of-order multi-issue processor includes an instruction decode unit arranged to decode the window management instruction. A plurality of register windows are indexed by a current window pointer, and a working copy of the current window pointer is stored in a register in the instruction decode unit. The instruction decode unit uses the working copy of the current window pointer to handle the window management instruction.

The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.

An arithmetic processing unit includes a register file provided with multiple register windows, an arithmetic executor executes an instruction with data retained in the register file as an operand, and a current window pointer which retains address information specifying a register window which becomes a current window, and a controller. The controller controls the address information retained by the current window pointer is updated, when a window switching instruction for indicating switching of the current window has been decoded. The arithmetic executor reads data in a first register window specified by the address information before being updated and data in a second register window specified by the updated address information from the register file, after the decoding of said window switching instruction has been started until commit of the window switching instruction is started.

A target computing system (10) is adapted to support a register window architecture, particularly for use when converting non-native subject code (17) instead into target code (21) executed by a target processor (13). A subject register stack data structure (an ''SR stack'') (400) in memory has a plurality of frames (410) each containing a set of entries (401) corresponding to a subset of subject registers (502) of one register window (510) in a subject processor (3). The SR (10) stack (400) is accessed by the target code (21) executing on the target processor (13). The SR stack (400) stores a large plurality of such frames 410 and thereby avoids overhead such as modelling automatic spill and fill operations from the windowed register file of the subject architecture. In one embodiment, a target computing system (10) having sixteen general purpose working registers is adapted to support a register window architecture reliant upon a (15) register file containing tens or hundreds of subject registers (502).

The invention relates to the technical field of wireless communication, and particularly relates to a method for inhibiting a high peak-to-average power ratio of an FBMC-OQAM system. The method comprises the following steps: searching a phase factor of a first section in D sections; calculating optimal phase factor vectors of inner layers of all data blocks; searching phase factor vectors of outerlayers; and multiplying the obtained phase factor vectors of inner layers with the phase factor vectors of outer layers at corresponding positions to obtain the finally necessary optimal phase factorvector. According to the method, the phase factors are divided into odd and even vectors to iterate separately, thereby enlarging the search range and seeking the optimal solution, then in combination with the FBMC-OQAM system, the overlapped parts of the data blocks are used, so that the phase factor vector with the minimum PARP of the sum of a weighted signal of the current symbol block and thesignal in a register window is used as the optimal phase factor vector, then the performance of the PAPR is inhibited without increasing the calculation amount.

In a data processing apparatus using a register window method performing data transmission from a master register to a work register during an exception handling, detecting a trap, discriminating whether or not a data transmission is required for the global registers by the trap, and transmitting data from the master register to the work register for only the global registers if the trap requires transmitting data for the global registers, thereby providing the data processing apparatus performing data transmission to the global registers if the occurring trap requires data for the global registers.

The invention relates to the technical field of computer hardware modeling. The invention provides a GPU-oriented parameter management method based on SystemC. The method comprises the following steps: step 1, executing barrier/lock management, calculating a new barrier state according to the current barrier state and the FIFO state, when judging that the GraphRegLock is 0, outputting the GraphRegLock to a graphic management module (2) through a transaction-level interface, and executing the step 2, otherwise, outputting the GraphGrawLock to a register window management module (3) through thetransaction-level interface when the GraphGrawLock is 0 and the GraphFunction is 0, and executing the step 3; Step 2, executing graph drawing command parameter and function code parameter management;And step 3, executing read-write management of register parameters.