38 results about "Bus error" patented technology

A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.

A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.

The invention relates to a multi-intelligent stand-alone servo control system based on dual redundant CAN bus communication. A main servo control drive receives the instruction of a host computer, so as to carry out corresponding operation. The instruction received by the host computer is redundantly sent to a servo control drive through a first CAN bus and a second CAN bus, wherein the first CAN bus and the second CAN bus are peer to each other. An instruction operation result and measurement parameters are fed back to the host computer, wherein the instruction operation result and the measurement parameters are sent by the main servo control drive in the system and an auxiliary servo control drive. Without increasing additional data transmission, bus error self-diagnosis and bus state self-diagnosis are carried out on the dual redundant CAN buses are in real time. When communication bus abnormities are found through self-diagnosis, corresponding self-recovery measures are taken for self-recovery. The system is used for the communication of different intelligent stand-alones of a rocket flight control servo system, realizes highly reliable communication with relatively low cost, has the functions of self-diagnosis and self-recovery, and ensures the high reliability of a rocket and other flight control systems.

The invention relates to a computer system and a method for monitoring a bus of the computer system. The system comprises a master device, a slave device, a back plate bus and a bus timer, wherein themaster device is connected with the slave device by the back plate bus. The back plate bus comprises an address latch enabling signal line and a bus error signal line, wherein the address latch enabling signal line is used for transmitting an address latch enabling signal, and the bus error signal line is used for transmitting a bus error signal. The computer system also comprises a bus monitoring unit, wherein the bus monitoring unit is connected with the address latch enabling signal line and the bus error signal line and used for starting the bus timer to time when receiving the bus address latch enabling signal by the address latch enabling signal line and for transmitting the bus error signal by the bus error signal line when the bus timer is overtime.

A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.

In a bridge which connects between an expansion bus of a primary system and that of a secondary system, a local error such as an expansion bus error and CPU hang-up which occurs in the secondary system is recognized. The primary system is notified of the local error as a system error.

Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes a symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code scheme for transfer over a bus in two or more transfers. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol correcting code H-matrix framework is defined including specifying bit positions for the original checkbits and for additional checkbits associated with a symbol correcting code. The bit positions are specified such that the additional checkbits are in bit positions that are transferred over a bus in a transfer subsequent to a first transfer. A symbol correcting code H-matrix is created using the bit positions indicated by the framework by iteratively adding rows of H-matrix bits on a symbol column basis such that the symbol correcting code H-matrix describes the symbol correcting code, and the Hamming distance n code is preserved as a subset of the symbol correcting code H-matrix.

A computer system includes an interrupt controller to notify a bus error occurrence, and a multithreaded processor. The multithreaded processor includes a schedule register that settles a sequence of performing a plurality of virtual CPUs and stores data for virtual CPUs to be performed, and a virtual CPU execution portion that performs virtual CPUs according to a sequence settled by the schedule register. Virtual CPUs operate different operating systems (OS's) and include a first virtual CPU that operates a management OS to manage other OS's. When notified of bus error occurrence, the virtual CPU execution portion operates only the first virtual CPU regardless of an execution sequence settled in the schedule register. The first virtual CPU reinitializes a bus where an error occurred.

A peripheral bus error containment and recovery system enables a bus device to experience a fatal bus error and recover without stopping execution of an operating system. When a fatal bus error is detected at the bus device, a bus controller may deactivate a data link layer for a downstream port populated by the bus device, causing an operating system device driver to be uninstalled for the bus device. Then, the operating system device driver may be reinstalled without physically removing the bus device.

The invention discloses a 1553B bus monitoring system which comprises a 1553B bus isolation transformer, a 1553B bus transceiver and a programmable logic device. After a 1553B bus passes through the 1553B bus isolation transformer and the 1553B bus transceiver, a pair of logically complementary digital signals are output; filter shaping, code stream extraction and protocol analysis and processing are conducted on the input digital signals through the programmable logic device and extracted word information and timestamp information of the 1553B bus are written in a computer memory. With regard to normal 1553B bus transmission, all command word information, control word information, data word information and interval time information of the adjacent words can be monitored and recorded by the monitoring system, wherein the command word information, the control word information, the data word information and the interval time information of the adjacent words are transmitted on the 1553B bus. With regard to abnormal 1553B bus transmission, when a bus transmission abnormality occurs, a bus fault type, a fault occurrence time point and recorded position information when a fault occurs can be monitored and recorded by the monitoring system.

The invention discloses an autonomous error correction management method for a CAN bus of a space vehicle. The CAN bus is composed of a master node and N slave nodes; Autonomous recovery management and autonomous recovery management of bus network errors by the master node; the autonomous recovery management of bus errors by the master node means that the master node regularly detects all channel buses and performs autonomous error correction on channel buses that do not meet the standards; The self-recovery management of the bus error by the slave node refers to that the slave node detects its own channel bus and performs autonomous error correction on the channel bus that finds an error; the self-recovery management of the bus error by the master node refers to The proportion of slave nodes with continuous communication abnormality detected in the period T5 is higher than the standard proportion, and an instruction is sent to start troubleshooting and diagnosis.

Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input / output (I / O) subsystem formed by a plurality of I / O devices communicating via the bus, includes categorizing, in a recursive manner, the I / O subsystem, and isolating a source of an error condition within the I / O subsystem. Further, the I / O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input / output mechanism, coupled to the processing mechanism.

The invention provides a power supply controller and a direct grid-connected control method, the power supply controller comprises an S3R, a BCDR and a bus error amplifier, the S3R is connected with a first bus error amplifier, and the BCDR is connected with a second bus error amplifier. The method has the advantages that the BCDR and the S3R are provided with the independent bus error amplifiers, loop design decoupling of the BCDR and the S3R is achieved, the design is more flexible, the dynamic characteristic and stability of the bus are improved, and the power expansion capacity is enhanced; through the direct grid-connected control method of the dual power supply controllers, the power expansion capability of the power supply controllers is further improved, the grid-connected method does not need to add an independent grid-connected controller single machine, so that power expansion can be performed under the condition of not additionally increasing the weight of the whole satellite, and the method can be expanded and applied to grid-connected control of multiple power supply controllers.

The invention provides a bus error recovery processing method, which belongs to the technical field of CAN bus. It solves the problem that it is difficult for the existing bus nodes to return to the normal working state when an error occurs and enters the bus off state. In this bus error recovery processing method, the node detects an error and enters the operation of error recovery processing after it enters the "bus off state" and includes the following steps: The error count control node is in the corresponding state; b. The main controller control node is disconnected from the CAN bus; c. Keep the disconnection time T0, and enter step d after the timing T0 is full; d. The main controller controls the CAN controller to restart ; e. The CAN controller monitors the level signal on the CAN bus. The bus error recovery processing method has the advantage of timely checking the errors detected on the nodes.