Computer system and method for monitoring bus of same

Abstract

The invention relates to a computer system and a method for monitoring a bus of the computer system. The system comprises a master device, a slave device, a back plate bus and a bus timer, wherein themaster device is connected with the slave device by the back plate bus. The back plate bus comprises an address latch enabling signal line and a bus error signal line, wherein the address latch enabling signal line is used for transmitting an address latch enabling signal, and the bus error signal line is used for transmitting a bus error signal. The computer system also comprises a bus monitoring unit, wherein the bus monitoring unit is connected with the address latch enabling signal line and the bus error signal line and used for starting the bus timer to time when receiving the bus address latch enabling signal by the address latch enabling signal line and for transmitting the bus error signal by the bus error signal line when the bus timer is overtime.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a computer system and a bus monitoring method of the computer system. Background technique [0002] Computer systems are widely used in IT, telecommunications, industrial control, transportation, aerospace and other fields. The backplane bus in the computer system is used to realize the connection of different types of devices, and it is a set of transmission lines that provide signal transmission for multiple functional components. Computer systems in different application fields and occasions have different forms of backplane buses. [0003] With the development of computer technology and network technology, the backplane bus has experienced the development of parallel buses such as VME, ISA / PCI, and point-to-point interconnections such as PCI-E. Moreover, with the development of technology in the security field, such as industrial control, transportation, aerospace and oth...

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Problems solved by technology

[0006] In the process of realizing the present invention, the inventor finds that the prior art has at least the following disadvantages: at least 82 VME bus signal lines are required in the computer system, which is a large number and increases the volume of the system; The chip is completed and the cost is high

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