Method and manufacturing low leakage MOSFETs and FinFETs

Abstract

By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation / relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

Description

FIELD OF THE INVENTION [0001] The present invention relates to the fabrication of integrated circuits and, more specifically, a method for fabricating field effect transistors (FETs) wherein source-drain current flows along a (100) crystal plane. BACKGROUND [0002] Semiconductor integrated circuit chips are constructed as dice on wafers. A typical wafer material is crystalline silicon. Wafers are cut from single crystal silicon ingots grown from polysilicon by means of, for example, Czochralski method (CZ) crystal growth. CZ wafers are preferred for VLSI applications as they can withstand high thermal stresses and are able to offer an internal gettering mechanism that can remove unwanted impurities from device structures on a wafer surface. This also gives the wafer a uniform internal structure based on silicon's diamond cubic lattice structure. Although the diamond cubic lattice provides strength and rigidity to the wafer, defects in the crystal lattice, for example, slip dislocatio...

AI Technical Summary

Benefits of technology

[0008] By aligning the primary flat (or notch) of, for example, an epi wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation / relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. Leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique, the leakage current is reduced by up to two orders of magnitude for an n-channel CMOS device.

[0011] An improvement in MOSFET performance and yield has been observed by incorporating the present invention into the MOSFET fabrication process. By aligning the MOSFET channel so that source-drain channel current flows in the (100) plane, manufacturing related defects and related leakage and parasitic currents are reduced. Another application of various embodiments of the present invention is in the fabrication of a specific type of MOSFET device called a FinFET. A FinFET is a MOSFET with a raised current channel (fin) that utilizes a gate electrode on at least three sides of the channel. Aligning the fin with the (100) plane results in a reduction in capacitance between the gate electrode and FinFET channel and body, and superior electrical isolation between the gate electrode and FinFET channel and body. A further benefit of this fabrication method utilizing a (100) channel direction is that the corners of the gate electrode are inherently rounded, reducing local electric fields and consequently increasing the breakdown voltage and improving uniformity of an electric field in a gate dielectric. Additionally, the (100) channel direction fabrication method described herein reduces stress in silicon “corners.” This benefit is especially pronounced during high temperature processing (e.g., during growth of a thermal silicon dioxide gate dielectric). One result of the reduction in stress is that, for example, less boron p-type doping atoms diffuse out of corner regions into any adjacent existing oxide or growing oxide. There is thus less segregation of the boron into the silicon dioxide. Silicon corner regions maintain a higher doping concentration and, hence, a higher MOS threshold voltage for formation of a parasitic channel in the finished device. Reduction or elimination in the formation of the parasitic channel at low MOS gate voltages produces a substantial reduction in leakage current of the device.

Problems solved by technology

As MOSFETs are scaled to channel lengths below about 200 nm, conventional MOSFETs suffer from several problems.

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