Spatially-arranged chemical processing station

Abstract

The present invention discloses a station, e.g., for IC fabrication with a flexible configuration. It consists of an array of processing chambers, which are grouped into processing modules and arranged in a two-dimensional fashion, in vertical levels and horizontal rows, and is capable of operating independent of each other. Each processing chamber can perform electroless deposition and other related processing steps sequentially on a wafer with more than one processing fluid without having to remove it from the chamber. The system is served by a single common industrial robot, which may have a random to access to all the working chambers and cells of the storage unit for transporting wafers between the wafer cassettes and inlet / outlets ports of any of the chemical processing chambers. The station occupies a service-room floor space and a clean-room floor space. The processing modules and the main chemical management unit connected to the local chemical supply unit occupy a service-room floor space, while the robot and the wafer storage cassettes are located in a clean room. Thus, in distinction to the known cluster-tool machines, the station of the invention makes it possible to transfer part of the units from the expensive clean-room area to less-expensive service area.

Description

FIELD OF THE INVENTION [0001] The present invention relates to semiconductor manufacturing equipment. More particularly, the invention relates to a spatially-arranged station for deposition from liquid media, e.g, to an electroless deposition station that contains a plurality of individual and independently operating chemical processing chambers served by a common workpiece handling unit. The station of the present invention may find use in the mass production of high density interconnect for integrated circuits. BACKGROUND OF THE INVENTION [0002] In present ULSI (ultra-large-scaled-integration) structures, high circuit speed, high packing density and low power dissipation are essential. As a result, feature sizes must be scaled downward, and the interconnect related time delays become the major limitation. Elemental aluminum and its alloys have been the traditional metals used to form lines and plugs in IC's; however, aluminum has a relatively high resistivity and its electromigrat...

AI Technical Summary

Benefits of technology

[0014] It is an object of the present invention to provide a processing station that contains a plurality of individual and independently operating processing chambers arranged in multiple-level manner vertically and in linear rows horizontally with transfer of objects by means of by a common workpiece handling unit. It is another object is to provide the aforementioned station suitable for electroless deposition in the mass production of semiconductor wafers with high interconnect density. A further object is to provide the aforementioned station which is universal in use, flexible for restructuring in accordance with specific production requirements, highly efficient in production due to parallel operation of a plurality of chemical processing chambers in accordance with a required sequence, and occupying a reduced floor area due to the use of a common industrial robot for transferring objects between the service area and the equipment of the clean room. It is another object to provide the aforementioned station in which a maximum possible amount of equipment units can be transferred from the clean room to the service area thus reducing the floor space occupied by the equipment in the clean-room area. It is a further object to provide a chemically processing station with spatial arrangement of interacting station units, such as processing modules, wafer cassettes, and a wafer-handling unit.

[0020] 4. Each processing chamber is able to perform different processing steps with different chemicals without the need of moving the wafer to a different processing chamber.

[0026] 10. The new system configuration results in the smallest possible equipment size for a relatively slow process than any other electroless deposition tool; this design will also result in lower cost and higher system reliability.

Problems solved by technology

As a result, feature sizes must be scaled downward, and the interconnect related time delays become the major limitation.

Elemental aluminum and its alloys have been the traditional metals used to form lines and plugs in IC's; however, aluminum has a relatively high resistivity and its electromigration susceptibility can lead to the formation of voids in the metal lines.

However, there are serious problems related to process integration of copper to integrated circuits.

It is difficult to pattern and remove copper by dry etching, because its reaction product is not gaseous.

The conventional approach of depositing a film and then patterning it cannot be relied upon for producing copper interconnections on substrates.

Another problem lies in copper's extremely high diffusivity in silicon dioxide, and minute amount of diffused copper atoms in the transistors' active regions will play havoc with their device characteristic.

There is great difficulties to fill them using conventional means.

However, it is apparent that the electroplating technique has its limitations in further scaling down the geometry of the device.

Utilization of a limited number of discrete contact with the seed layer at the perimeter of the wafer usually produces higher current densities at the contact points than at other portion of the wafer; non-uniformity of voltage drop on the wafer surface in turn causes non-uniformity in the deposits of plated material's thickness.

Although this non-uniformity can be compensated by the provision of additional electrically conductive elements at the wafer periphery, it adds to the complexity of equipment, and increases costs of production.

As a result, it becomes more difficult to provide continuous barrier and particularly seed layers.

In addition, the thickness ratio of the seed layers in the trenches will become disproportional larger as compared to the copper layer thickness in the trenches; keeping this ratio constant will aggravate the non-uniformity of the electroplated film.

Since single wafer and clustered system for IC processing has become the common and prevailing trend in the IC industry, big open tanks with processing chemicals as required by the electroless plating process are not compatible or easily implemented in IC fabs, and are wasteful of the expensive ultra-clean fab. space because of their large footprint.

Both the electro- and electroless plating techniques suffer from a common problem because their operations usually taking place in open electrolyte baths.

When wafers are transferred from the baths to be cleaned, foreign particles tend to be deposited on the surface of the substrate and oxidation of the catalytic surface in the exposure to air may result in poor catalytic activity and poor metal deposits.

Another common problem is the possible occurrence of non-wetting of deep and narrow trenches or holes in the substrate surface because of liquid evaporation.

In spite of their advantages, the embodiment for a single wafer chamber suffers from the shortcoming of low wafer throughput and would be unsuitable for the manufacturing environment.

Their batch processing embodiment, on the other hand would have a issue of film thickness uniformity control within the wafer and from wafer to wafer.

Such an arrangement is purely linear and cannot rationally use the floor space of the clean room.

A disadvantage of the aforementioned arrangement that the entire cluster machine can be placed into the clean room only as an indivisible or integral system which does not allow placement of those units which otherwise could be placed into a service area beyond the boundaries of the expensive clean-room floor space.

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