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Microelectronic packages with solder interconnections

a micro-electronic and interconnection technology, applied in the direction of printed circuit aspects, sustainable manufacturing/processing, final product manufacturing, etc., can solve the problems of thermal fatigue stress on the solder bond in such assemblies temperature rise and fall of the assembly, etc., to achieve enhanced flexibility and fatigue resistance, the effect of relieving the stress on the bond

Inactive Publication Date: 2006-06-01
TESSERA INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010] In a particularly preferred method according to this aspect of the invention, the first element includes a dielectric packaging structure having an interior surface facing toward the second element and having an exterior surface. The pads of the first element are disposed on the interior surface. The packaging structure further includes terminals exposed at the exterior surface which are electrically connected to the pads on the interior surface. Desirably, the second element includes one semiconductor chip or a plurality of semiconductor chips. Preferred methods according to these embodiments of the invention, thus can provide packaged microelectronic elements, such as packaged semiconductor chips, incorporating the microelectronic element and an interposer having terminals connected to the microelectronic element by elongated solder columns. Such an assembly can be utilized by bonding the terminals of the interposer to a circuit panel or other substrate. The assembly can be handled and mounted using standard techniques. The elongated solder columns provide enhanced resistance to stress as compared to standard flip-chip mountings, but without the need for special techniques during assembly of the chip to the circuit panel.
[0012] A further aspect of the present invention provides methods of making solder connections which include the steps of providing first and second elements having confronting surfaces and having pads on the confronting surfaces arranged in pairs, each pair including a pad on one element and a pad on the other element, and providing solder masses at at least some of the pairs so that each such solder mass is in contact with both pads of the pair. Methods according to this aspect of the invention also include the step of moving the elements away from one another through a preselected vertical movement so as to stretch the solder masses while the solder masses are at a temperature above the recrystallization temperature of the solder but below its recrystallization temperature. In methods according to this aspect of the invention, the solder masses incorporate columnar inclusions, which are present when the solder masses are stretched. As used in this disclosure, the term “columnar inclusion” refers to a separate phase within the solder present as elongated droplets or particles. For example, the moving step may be performed at least in part at a temperature between the solidus and liquidus temperatures of the solder masses, and the columnar inclusions may be present as solid inclusions within the partially molten solder masses during the moving step. Such columnar inclusions will be formed, for example, by lead-tin alloy solders containing about one percent to about five percent copper by weight. As the solder masses are stretched during the moving step, the columnar inclusions tend to orient preferentially in the direction of movement, and hence orient along the long axis of the elongated solder masses resulting from the moving step. Columnar inclusions further enhance resistance of the elongated solder masses to fatigue failure.
[0015] Yet another aspect of the invention provides packaged microelectronic elements such as semiconductor chips. A packaged microelectronic element according to this aspect of the invention includes a microelectronic element such as a semiconductor chip together with an interposer overlying the contact-bearing surface of the chip. The interposer desirably is a flexible sheetlike element and includes an interior surface facing toward the chip and pads on the interior surface. The interposer further includes terminals exposed for connection to external components. The terminals may be exposed at an exterior surface of the interposer, facing away from the chip. The terminals are electrically connected to the pads over the interposer. The pads of the interposer in turn are electrically connected to the pads of the microelectronic element to a semiconductor chip by elongated solder masses extending between the pads of the interposer and the pads of the micro electronic element chip. Most desirably, the assembly includes a compliant dielectric layer such as a gel, foam or elastomer surrounding the elongated solder masses. Such an assembly can be handled and the amount of using standard surface mounting techniques, as by solder bonding the terminals of the interposer to a circuit panel or other substrate. After assembly, flexure of the elongated solder masses provides compensation for differential thermal expansion, and relieves stress on the bonds between the terminals and the circuit panel.

Problems solved by technology

The solder bonds in such assemblies typically are subjected to thermal fatigue stress during manufacture and during use of the assembly.
The electrical power dissipated within the chip and other elements of the assembly tends to heat the chip and the circuit panel, so that the temperatures of the chip and circuit panel rise and fall depending on use of the device.
Processing operations during manufacturing also cause the temperature of the assembly to rise and fall.
Differential expansion and contraction causes the contact pads on the chip to move relative to the contact pads on the substrate, which in turn tends to strain the solder bonds.
The barrel-shaped solder bonds resulting from conventional C4 bonding techniques are susceptible to failure under these conditions.
Chip mounting procedures using elongated solder columns heretofore have suffered form considerable drawbacks.
These procedures require specialized techniques and considerable care during mounting of the chip to the circuit panel.
Moreover, these procedures require handling and testing of bare, unpackaged semiconductor chips.
It is difficult to test such a bare chip prior to attachment of the chip to the circuit panel.
Moreover, the bare chip is susceptible to damage during handling and testing.

Method used

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Embodiment Construction

[0026] A process in accordance with one embodiment of the invention utilizes a flexible dielectric sheet 20 having oppositely facing inner surface 22 and outer surface 24. Sheet 20 may be formed from the polymeric materials such as a polyimide. The thickness of sheet 20 is greatly exaggerated in FIG. 1 for clarity of illustration. Typically, sheet 20 is about 25-100 μm thick. Sheet 20 has numerous holes extending through it. These holes are provided with metallic via liners 26. Each via liner defines a pad 28 on the inner surface 22 of the sheet. Each via liner is also exposed at the outer surface 24 of the sheet. Sheet 20 is attached to a ring-like frame 27 formed from a rigid material. The sheet may be stretched on the frame in the manner disclosed in U.S. Pat. No. 5,518,964, the disclosure of which is hereby incorporated by reference herein and in the manner discussed in U.S. Pat. No. 6,217,972, the disclosure of which is also incorporated by reference herein. As described in suc...

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Abstract

A soldered assembly for a microelectronic element includes a microelectronic element, solder columns extending from a surface of the microelectronic element and terminals connected to distal ends of the columns. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] The present application is a continuation application of U.S. patent application Ser. No. 09 / 854,269, filed May 11, 2001, which application is a divisional of U.S. patent application Ser. No. 09 / 157,047, filed Sep. 18, 1998, now U.S. Pat. No. 6,335,222, the disclosures of which are hereby incorporated by reference herein. Said '047 application also claims benefit of the filing date of U.S. Provisional Patent Application No. 60 / 059,225, filed Sep. 18, 1997, the disclosure of which is hereby incorporated by reference herein.BACKGROUND OF THE INVENTION [0002] Microelectronic elements such as semiconductor chips have been connected to circuit panels by soldering. One technique which has been utilized heretofore is referred to as “flip chip” bonding. In flip chip bonding, the front surface of the chip bearing the contact pads of the chip faces downwardly, towards the surface of a circuit panel having a pattern of pads matching the pattern of...

Claims

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Application Information

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IPC IPC(8): H01L23/48H01L23/28H01L21/56H01L21/60H05K3/34
CPCH01L21/561H01L21/563H01L21/568H01L21/6835H01L23/3114H01L23/49805H01L23/49811H01L24/11H01L24/12H01L24/16H01L24/29H01L24/742H01L24/81H01L24/94H01L2224/11003H01L2224/1184H01L2224/131H01L2224/13111H01L2224/274H01L2224/29298H01L2224/73203H01L2224/81801H01L2924/01002H01L2924/01005H01L2924/01013H01L2924/01015H01L2924/01018H01L2924/01027H01L2924/01029H01L2924/01042H01L2924/0105H01L2924/01078H01L2924/01082H01L2924/18301H05K3/3436H05K3/363H05K2201/0215H05K2201/0248H05K2201/09427H05K2201/10977H05K2203/0465H05K2203/074H05K2203/306H01L2924/00013H01L2924/01006H01L2924/01023H01L2924/01033H01L2924/014H01L2224/29101H01L24/27H01L2224/02319H01L2224/02333H01L2224/0401H01L2224/13099H01L2924/00H01L2924/3512H01L2224/29099H01L2224/29199H01L2224/29299H01L2224/2929H01L2924/12042Y02P70/50
Inventor DISTEFANO, THOMAS H.
Owner TESSERA INC
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