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Dielectric layer of ultra-low dielectric constant and forming method thereof

A technology with ultra-low dielectric constant and low dielectric constant, which is applied in the direction of circuits, electrical components, electric solid devices, etc., and can solve the problem of poor adhesion, poor step coverage of metal dielectric barrier layers, and influence on metallization process Electrical performance and reliability and other issues, to achieve the effect of good electrical performance and reliability, low tensile stress

Active Publication Date: 2009-03-25
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the interface between the porous low-k dielectric layer 604 and the dielectric barrier layer 602 or the interface with the capping layer 606 formed by a typical deposition process has poor adhesion, usually less than 5 Joules. / square meter
In the subsequent etching process, due to the lack of mechanical strength and the difference in etching selectivity, the interface between the porous low-k dielectric layer and the dielectric barrier layer, or the porous low-k dielectric layer The interface with the silicon oxide top layer produces lateral etching (as shown in D and C areas in the figure), and the Kink Profile Issue (Kink ProfileIssue) is derived, which makes the subsequent metal dielectric barrier layer deposited in the double damascene opening step Poor coverage leads to the formation of holes (Viod), which in turn affects the electrical performance and reliability of the metallization process

Method used

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  • Dielectric layer of ultra-low dielectric constant and forming method thereof
  • Dielectric layer of ultra-low dielectric constant and forming method thereof
  • Dielectric layer of ultra-low dielectric constant and forming method thereof

Examples

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no. 1 example

[0065] In this embodiment, the temperature change program is a gradient temperature change program including two temperature stages, such as figure 2 shown. exist figure 2 Among them, the two temperature stages include a first temperature stage 20 and a second temperature stage 22 in sequence, wherein the first temperature stage 20 is a high temperature stage; the second temperature stage 22 is a low temperature stage. The temperature of each stage 20, 22 is related to the dielectric matrix (DielectricMatrix) used. In one embodiment, the temperature of the first temperature stage 20 is, for example, between 250 and 350 degrees Celsius; the temperature of the second temperature stage 22 is, for example, between 200 and 250 degrees Celsius. In one embodiment, the same main chain precursor and the same porogen are introduced during the deposition process of the first temperature stage 20 and the second temperature stage 22 .

[0066] Each stage 20, 22 can be performed on-sit...

no. 2 example

[0073] In this embodiment, the temperature change program is a gradient temperature change program including two temperature stages, such as image 3 shown. exist image 3 Among them, the two temperature stages include a first temperature stage 30 and a second temperature stage 32 in sequence, wherein the first temperature stage 30 is a low temperature stage; the second temperature stage 32 is a high temperature stage. The temperature at each stage 30, 32 is related to the dielectric substrate used. In one embodiment, the temperature of the low temperature stage is about 200 to 250 degrees Celsius; the temperature of the high temperature stage is about 250 to 350 degrees Celsius. In one embodiment, when performing the deposition process in the first temperature stage 30 and the second temperature stage 32, the same main chain precursor and the same porogen are introduced.

[0074]Each stage 30, 32 can be performed on-site in the same deposition tool or off-site in a differe...

no. 3 example

[0080] In this embodiment, the temperature change program is a gradient temperature change program including three temperature stages, such as Figure 4 shown. exist Figure 4 Among them, these three temperature stages include the first temperature stage 40, the second temperature stage 42 and the third temperature stage 44 carried out in sequence, wherein, the first temperature stage 40 is a low temperature stage; the second temperature stage 42 is a high temperature stage stage; the third temperature stage 44 is also a low temperature stage. The temperature of the second temperature stage 42 is higher than the temperature of the first temperature stage 40 and the third temperature stage 44 . The temperatures of the first temperature stage 40 and the third temperature stage 44 can be the same or different, and only the first temperature stage 40 and the third temperature stage 44 having the same temperature are shown in the figure. The temperature at each stage is related ...

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Abstract

The invention relates to a method for forming an ultra-low dielectric constant dielectric layer. The method is characterized in that the reaction of a dielectric substratum added for deposition is triggered by the regulation of temperature-varying program or pressure-varying program in the process of deposition so as to allow the ultra-low dielectric constant dielectric layer, which is porous, multi-layered and provided with a density gradient, to be formed on the barrier layer of the substratum.

Description

technical field [0001] The present invention relates to a dielectric layer and its forming method, and in particular to an ultra-low dielectric constant dielectric layer and its forming method. Background technique [0002] With the rapid development of integrated circuit technology, more and more attention has been paid to the back-end metal interconnection and low dielectric constant material technology. When the process develops to the field of deep sub-micron components, the RC delay phenomenon caused by the metal interconnection seriously affects the speed of device operation. A method for improving the RC delay may be to use a material with a low dielectric constant as the material of the insulating layer between the multilayer metal interconnections, thereby reducing the parasitic capacitance between the metal layers. [0003] The porous low-k dielectric layer is a dielectric material containing multiple pores. Since the air with a dielectric constant of only 1 is a...

Claims

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Application Information

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IPC IPC(8): H01L21/31H01L21/768H01L23/532
Inventor 陈美玲宋述仁黄建中
Owner UNITED MICROELECTRONICS CORP
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