Tech. for etching capable of controlling grid structural length

Abstract

The invention relates to an etching process able to control the length of a grid structure, using hard mask to raise the selection ratio of etching polycrystalline silicon layer, and adopting three-stage etching (first primary etching / second primary etching / over etching) in the polycrystalline silicon layer etching process; the first primary etching gas contains carbon tetrafluoride to reinforce the whole patternized hard mask and high molecular film deposit on the side walls of the polycrystalline silicon layer to convert the high molecular film deposit into high molecular film combination; the high molecular film combination can effectively resist the side corrosion of halides to the polycrystalline silicon layer to make the horizontal width of the polycrystalline silicon layer unable to be reduced, and the patternized hard mask can better resist the corrosion of the etching gas to hold the pattern, thus solving the problem of generating initial creepage.

Description

technical field [0001] The invention relates to an etching process capable of controlling the length of a gate structure, in particular to a process for etching a polysilicon layer by using a patterned hard mask layer as a mask. Background technique [0002] Dry etching is basically a process of selectively removing the thin film layer deposited on the chip by using the photoresist produced by photolithography as a mask. The most important condition to measure the success of this project is to be able to completely transfer the pattern size of the photoresist to the etched film 100% without error, especially the etching of the gate, which is even more important, because MOS The initial voltage and saturated drain current of the transistor depend on the length of the gate channel and the width of the gate photoresist. [0003] The usual technology is to perform a typical breakthrough step (open step), main etching step (main etch) on a structure (patterned photoresist / anti-r...

AI Technical Summary

Problems solved by technology

For example, when the thickness of the patterned photoresist is not enough to leave enough on the anti-reflection barrier layer before the gate etching is completed, the CD of the gate may be reduced, resulting in Occurrence of Sub-threshold Leakage of MOS transistors

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