Method for reducing oxidation erosion of grid stack layer

Abstract

A method for reducing grid stacked layer oxidation erosion is to insert nitrogen ions onto sidewall surface of the grid stacked layer by tilt ion insertion method, so the sidewall surface is full of nitrogen ions, then oxygen annealing is undergone to form a silicon nitride oxigen layer on the grid stacked layer sidewall surface to stop continued oxidation of the polysilicon on the grid stacked layer, which can not only avoid thickenss increase on the dielectric edge resulted in oxidation erosion of the polysilicon layer, but also eliminate polysilicon remains.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor memory, and in particular to a method for reducing oxidation erosion of gate stack layers. Background technique [0002] As computer microprocessors become faster and faster, the amount of data calculations performed by computer software will become larger, and the demand for natural memory will also be higher. Random access memory (RAM) components have long been widely used in computers, but their data will be erased as the power supply is interrupted, so it is also called volatile memory; another component called non-volatile memory is Because its data will not disappear due to the interruption of power supply, it can be used in other different occasions, such as mask read-only memory (Mask ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read memory (EEPROM), etc. [0003] In addition, there is a non-volatile memory called flash memory, which...

AI Technical Summary

Problems solved by technology

However, although the long-term thermal oxidation process can remove polysilicon residues, it will cause the exposed parts of the first and second polysilicon layers to be oxidized and corroded, resulting in silicon oxide between the first and second polysilicon layers- The thickness of the edge part of the silicon nitride-silicon oxide (ONO) dielectric layer increases, which reduces the capacitive coupling ratio (Coupling ratio) between the control gate and the floating gate, which affects the ability of the floating gate to capture electrons, indirectly Affects the operational performance of flash memory cells

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