Manufacturing method of super junction device

Abstract

The invention discloses a manufacturing method of a super junction device. The method comprises the following steps: step 1, forming a gate structure which is a trench gate, filling a gate trench with a polysilicon gate in the formation process of the trench gate, and performing first flattening to enable the surface of a first epitaxial layer with the trench gate to be a flat surface, wherein the width of the gate trench at the leading-out position of the gate structure meets the requirement of forming a contact hole; step 2, forming a cap layer at the top of the trench gate under the condition that the gate oxide layer outside the gate trench is reserved; and step 3, forming a super junction in the first epitaxial layer which is provided with the cap gate and has the flat surface, and carrying out second flattening. According to the method, on the basis of realizing the full-flat process, the external expansion of doped impurities of the polysilicon gate and the damage to the gate oxide layer can be prevented at the same time.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a super junction device. Background technique [0002] The super junction is composed of alternately arranged P-type thin layers also called P-type pillars (Pillar) and N-type thin layers also called N-type pillars formed in the semiconductor substrate. Devices using super junctions are super junction devices such as super junction devices. junction MOSFET. The internal reduced surface electric field (Resurf) technology using P-type thin layer and N-type thin layer charge balance can increase the reverse breakdown voltage of the device while maintaining a small on-resistance. [0003] The pillar structure of the PN interval of the super junction is the biggest feature of the super junction. Currently, there are mainly two methods for manufacturing the pillar structure of the PN spacer, one is obtained by multiple epitaxy...

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Problems solved by technology

In this method, the polysilicon gate is formed before the super junction structure, which will directly expose the surface of the polysilicon gate after the first planarization, and the polysilicon gate is usually a heavily doped structure such as N-type heavily doped structure, at this time, the doping impurities of the polysilicon gate, such as phosphorus or arsenic, are prone to outspread (Out Doping) at high temperatures, especially in the process of silicon oxide film formation, because the solid solubility of P and As in the oxide layer is far away. Smaller than silicon, the thermal oxidation process has a repelling effect on P and As, resulting in the accumulation of N-type doping elements out of Out Doping in the polysilicon gate during the thermal oxidation process and diffusion on the Si surface; in addition, the gate dielectric on both sides of the polysilicon gate The top surface of the layer is also exposed, making the gate dielectric layer vulnerable to damage

[0022] An improved method is to etch the polysilicon gate in advance to form a groove after the formation of the polysilicon gate, and then use the ONO of the second hard mask layer to form the second hard mask layer defining the super junction trench. The bottom oxide layer in the structure is used to fill the groove and act as a cap layer on the top of the polysilicon gate. In this method, the bottom oxide layer is usually formed by a thermal oxidation process. The thermal process in the formation process of the bottom oxide layer itself will make the impurities of the polysilicon gate Outward expansion occurs. At this time, it cannot prevent the accumulation of impurities in the outer expansion of the polysilicon gate on the silicon surface, so it cannot form a good protective effect.

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