Ring gate nano CMOS structure and preparation method thereof

A nanometer and gate-around technology, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, transistors, etc., can solve the problems of many steps, high cost and complicated technology in the manufacture of gate-around nanowires/sheet field effect transistors, and reduce the production cost. Cost and process difficulty, enhanced performance and reliability, effect of reduced process

Pending Publication Date: 2021-04-27
张鹤鸣
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, the gate-all-around nanowire / sheet field effect transistor has many manufacturing process steps, complex technology, and higher cost than conventional CMOS.

Method used

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  • Ring gate nano CMOS structure and preparation method thereof
  • Ring gate nano CMOS structure and preparation method thereof
  • Ring gate nano CMOS structure and preparation method thereof

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Experimental program
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Embodiment 1

[0052] See image 3 , image 3 is a schematic diagram of a gate-all-around nano-CMOS structure provided by an embodiment of the present invention, wherein, image 3 (1), image 3 (3) is a sectional view of a side view, image 3 (2) is a partial sectional view of the front view. Based on the above reasons, the present embodiment provides a gate-all-around nano-CMOS structure, which includes nMOS and pMOS. The first gate electrode 30 of the structure 20, the pMOS includes a second nanobody structure 40 disposed on the semiconductor substrate 10 and a second gate electrode 50 surrounding the second nanobody structure 40, wherein the first nanobody structure 20 and the second nanobody structure The two nanobody structures 40 are formed of semiconductor materials of the same conductivity type; the first gate electrode 30 and the second gate electrode 50 are formed of conductive materials of the same work function. It should be emphasized that the thickness and doping concentra...

Embodiment 2

[0065] On the basis of the above-mentioned embodiments, this embodiment also provides a method for preparing a gate-all-around nano-CMOS structure. The method for preparing the gate-all-around nano-CMOS structure includes:

[0066] Step 2.1, selecting a semiconductor substrate 10;

[0067] Step 2.2, forming a first material stack and a second material stack on the semiconductor substrate 10;

[0068] Step 2.3, removing the sacrificial layer of the first material stack and the sacrificial layer of the second material stack to form the first nanobody structure 20 with the first source region 60 and the first drain region 70 at both ends, and A second nanobody structure 40 with a second source region 80 and a second drain region 90 disposed at both ends;

[0069] Step 2.4, forming a gate dielectric layer and a first gate electrode 30 and a second gate electrode 50 with the same work function around the first nanobody structure 20 and the second nanobody structure 40 to form nMOS...

Embodiment 3

[0089] See Figure 6a ~ Figure 6n , Figure 6a ~ Figure 6n It is a schematic diagram of the preparation process of stacking the same layer of gate-all-around nanowires / sheet CMOS provided by the embodiment of the present invention. Based on the above content, this embodiment also provides a preparation method of stacking the same layer of gate-all-around nanowires / sheet CMOS. The preparation method is illustrated by taking the nanowire / sheet (second material layer) as Si and the sacrificial layer (first material layer) as SiGe as an example. The preparation method includes:

[0090] Step 3.1, see Figure 6a , providing a semiconductor substrate 10 .

[0091] Specifically, semiconductor substrate 10 is bulk Si.

[0092] Step 3.2, epitaxially growing laminated materials.

[0093] The stacked material will be used to prepare nanowires / sheets of stacked gate-all-around nano-CMOS. The conductivity type of the stacked material can be n-type or p-type. According to the design req...

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Abstract

The invention discloses a ring gate nano CMOS structure and a preparation method thereof. The ring gate nano CMOS structure comprises an nMOS and a pMOS, and the ring gate nano CMOS structure is characterized in that the nMOS comprises a first nano body structure arranged on a semiconductor substrate and a first gate electrode surrounding the first nano body structure, wherein the pMOS comprises a second nanobody structure arranged on the semiconductor substrate and a second gate electrode surrounding the second nanobody structure, and the first nanobody structure and the second nanobody structure are made of semiconductor materials of the same conductivity type; the first gate electrode and the second gate electrode are formed of a conductive material having the same work function. According to the ring-gate nano CMOS, process steps for preparing the ring-gate nano CMOS are reduced, and the process flow is reduced, so process difficulty and the preparation cost can be reduced, and the performance and reliability of the ring-gate nano CMOS and an integrated circuit thereof can be improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a gate-around nanometer CMOS structure and a preparation method thereof. Background technique [0002] As the feature size of integrated circuits breaks through 10nm, the short channel effect will make the transistor performance very unstable. At the same time, the leakage current increases significantly due to the quantum tunneling effect, further deteriorating the performance of the device. Moreover, the fabrication process of transistors at the nanometer scale is more complicated, which makes it difficult for the development of Moore's Law. [0003] In order to suppress the short-channel effect, researchers have proposed a variety of new nano-device structures, including double-gate, triple-gate, and ring-gate. These structures are expected to improve the performance of MOSFETs as the size of MOSFETs continues to shrink. [0004] Among these novel device s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L27/092H01L27/088H01L21/336
CPCH01L29/66803H01L29/785H01L27/0886H01L27/0924
Inventor 张鹤鸣
Owner 张鹤鸣
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