Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The method takes a dielectric layer as a mask and etches and a same-type heavily-doped region around a back-etched groove and a partial thickness of opposite-type body region under the same-type heavily-doped region to form a contact hole with a required depth. The method is substantially a self-aligning contact holeetching process, so that the problem of contact hole alignment offset caused by process fluctuation is basically solved, it is ensured that the contact hole and a gate trench have very high alignmentprecision, the problem that impurity ions injected into the contact hole are diffused to a channel region after annealing in the later process is avoided, and the performance of the semiconductor device is improved. Besides, since the method is the self-aligning contact hole etching process, the contact hole can be etched without the assistance of a photomask plate, so that one photomask plate can be saved, and the production cost is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] At present, the technology of IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) and VDMOS (Vertical Double-diffused MOSFET, vertical channel double-diffused metal oxide transistor) is constantly innovating, and the size of power semiconductor devices is constantly being realized. Under the premise of shrinking, the excellent performance of power semiconductor devices is also guaranteed. [0003] In the manufacturing process of the existing trench type IGBT transistor, it is necessary to transfer the design pattern of the contact hole from the mask plate to the wafer by means of a photolithography process after the trench type gate is completed, but when transferring the pattern , it is necessary to align the lithography alignment mark on the mask...

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Problems solved by technology

[0004] With the continuous reduction of device size, the size of the active region needs to be continuously reduced, and the critical dimension (CD size) reserved for the contact hole and gate trench at the design end is also gradually reduced. The process process inevitably needs to consider the alignment accuracy with the gate trench. Therefore, for small-sized device structures, the fluctuation between processes is very likely to cause the distance between the contact hole and the gate trench to be too small. The impurity ions implanted in the contact hole will diffuse to the channel region after annealing, which increases the doping concentration of impurities in the channel region, which in turn increases the threshold voltage of the IGBT transistor and affects the performance of the final semiconductor device.

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