Preparation method of enhanced CMOS sensor light emitting diode unit structure

Abstract

The invention discloses a preparation method of an enhanced CMOS sensor light emitting diode unit structure. The preparation method comprises the following steps: P-type wafer cleaning and surface oxide layer stripping, oxide layer coating, masking, configuring a square window for an oxide layer, high energy ion beam surface treatment, Si corrosion, masking and configuring the square window for the oxide layer, N-type doping, oxide layer coating, masking and oxide layer opening, P-type doing, oxide layer corrosion, silicide barrier layer coating, masking and opening, silicide coating, annealing, removeing unreacted silicide and barrier layer, nitrided layer coating, oxide layer coating, masking and configuring a lead contact hole, metal coating, chemical mechanical grinding, oxide layer coating, masking, oxide layer corrosion and wired metal coating. According to the preparation method of the enhanced CMOS sensor light emitting diode unit structure provided by the invention, the preparation process is simple, the quantum conversion efficiency can be enhanced, and the cost can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to the field of image sensors, in particular to a method for preparing an enhanced CMOS sensor light emitting diode unit structure. Background technique [0002] CMOS image chips convert charge into voltage at the pixel level, and most of the functions are integrated into the chip. This allows all functions to operate from a single power supply and enables flexible image readout according to regions of interest or windowing. [0003] CMOS image sensors are basically embedded with system-on-chip (SOC) structures such as analog-to-digital conversion (ADC), correlated double sampling (CDS), clock generation, and voltage regulators, or image post-processing, etc. Functions, which were previously only functions of application system-level design. The current CIS is usually produced according to the 1P5M process from 180nm to the recent 55nm, which allows the pixel design to a...

AI Technical Summary

Problems solved by technology

[0011] Random needle-like surface in c-Si with low reflectivity and high absorption efficiency; whereas CIS pixels with small pitch size contain random but limited number of structures, leading to large deviations in pixel characteristics, such as PRNU (photoresponse non-uniformity), Not suitable for high-quality uniform 2D imaging capabilities

[0012] The absolute critical angle of the embedded chamfered Si structure is made strictly, which makes the preparation process complicated and costly, and the uniformity faces great challenges

[0013] In traditional design structures such as figure 1 ), because the surface of the si medium is flat, the light is reflected and refracted, and there is only one light absorption, the light absorption efficiency is low, and the quantum conversion efficiency is also low

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