Through silicon via (TSV) back surface exposure process

Abstract

The invention discloses a through silicon via (TSV) back surface exposure process. By retaining a substrate above a TSV during the grinding of the back surface of the substrate, the damage to an exposed part of the TSV and the substrate caused by a physical thinning process is avoided, and the ground surface of the substrate with high total thickness variation (TTV) has high surface smoothness, so that the consistency in the subsequent etching process is high. The substrate is etched by an etching solution with high selection ratio of the substrate to a medium layer through a first wet method, the situation of etching of the medium layer and a barrier layer on the TSV for the first time decides whether or not the substrate is etched for the second time and the third time, the exposed part of the TSV has an enough height, and a conductive column of the exposed part is protected from being damaged by the etching solution. A photosensitive material serves as a medium protection layer, and a final TSV exposure structure is etched in an exposure and development manner, so that the corrosion and oxidization of conductive column copper in the conventional process are avoided, and the subsequent processing steps are simplified.

Description

technical field [0001] The invention relates to a method for manufacturing or processing semiconductor or solid devices or parts thereof in the technical field of microelectronics, in particular to a TSV outcropping process for transmitting current between separate components in a microelectronic device by using metal 3D interconnection. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption continue to increase. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional interconnection gradually becomes the limit to improve ...

AI Technical Summary

Problems solved by technology

[0005] 1) In the prior art, the back of the wafer is directly thinned to the TSV conductive pillars by grinding. During the grinding process, conductive substances will be introduced into the surface of the wafer. The conductive substances may come from the abrasive contained in the abrasive Metallic substances or conductors inside TSV holes, such as copper ions, which will greatly reduce the minority carrier lifetime in the wafer substrate

[0006] 2) The traditional TSV outcropping method can easily cause mechanical damage to the head of the TSV conductive column, such as scratches, cracks, etc., which seriously affect the performance, reliability and yield of IC

[0007] 3) After the backside is thinned, a dielectric layer needs to be deposited, and the subsequent process of opening and etching to remove the dielectric layer after depositing the dielectric layer at the TSV head, the etching method used will corrode and oxidize the copper in the TSV hole , requires additional process to remove copper oxide, which has the disadvantages of low efficiency and high cost

[0008] 4) The most important thing is that the currently disclosed process is only suitable for TSV with small TTV (total thickness variation, surface height difference)

In reality, the TTV of IC products may be very large, and the level of different manufacturers is different

In this way, the outcrop height of TSV is required to be relatively large to ensure that all TSVs can have good electrical contact, and the traditional TSV outcrop method cannot meet the above requirements.

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