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Silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device

A power device, N-type technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problem that the breakdown voltage of the device is very sensitive and is larger than the on-resistance, etc., to improve the breakdown voltage and drift region concentration. , the effect of reducing the on-resistance and reducing the lateral size

Inactive Publication Date: 2013-03-13
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for this device structure, the position of the N-type buried layer is very sensitive to the breakdown voltage of the device; and the specific on-resistance is still relatively large

Method used

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  • Silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device
  • Silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device
  • Silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0040] A SOI-based PMOSFET power device, such as Figure 5 As shown, it includes an N-type SOI base formed by vertically bottom-up substrate layer 1, dielectric buried layer 2 and N-type SOI semiconductor layer 3; the N-type SOI semiconductor layer 3 is lightly doped N-type A semiconductor layer (N-type high-resistance region), which has a P-type well region 4; the other surfaces of the P-type well region 4 except the upper surface are all in contact with the N-type SOI semiconductor layer 3; the P-type well region has The dielectric groove 6 is filled with an insulating medium 9; the dielectric groove 6 is horizontally ( Figure 5 The surface of the P-type well region 4 on one side of the shown x direction) has a P-type heavily doped (P+) drain region 14, and the surface of the P-type heavily doped drain region 14 leads to the drain electrode (D) through the drain metal; the dielectric The top of the P-type well region 4 on the other lateral side of the groove 6 has an N-typ...

Embodiment 2

[0042] Such as Figure 6 As shown, on the basis of Embodiment 1, the N-type body region 5 extends into the top of the N-type SOI semiconductor layer 3, and the N-type heavily doped low-resistance region 13 merges into the N-type heavily doped body contact region 12 form the same N-type heavily doped body contact region 12 .

Embodiment 3

[0044] Such as Figure 7 As shown, on the basis of Example 1, the N-type body region 5 also has a second P-type heavily doped source region 11b, and the N-type heavily doped body contact region 12 is sandwiched between the P-type heavily doped source Between the region 11 and the second P-type heavily doped source region 11b, the lead end of the second P-type heavily doped source region 11b is electrically connected to the source electrode; the second P-type heavily doped source region 11b and the The surfaces of the P-type well region 4 and the N-type body region 5 between the N-type heavily doped low-resistance regions 13 have a planar gate structure 8, and the leading end of the planar gate structure 8 is electrically connected to the gate electrode. In this way, there is a certain distance between the N-type body region 5 and the N-type high-resistance region 13 in the lateral direction, so as to provide a conduction current channel. Compared with the structures of Exampl...

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Abstract

The invention relates to a silicon on insulator (SOI)-based metal-oxide-semiconductor field-effect transistor (PMOSFET) power device and belongs to the technical field of power semiconductor devices. An N type SOI rib is adopted for the SOI-based PMOSFET power device so that the SOI-based PMOSFET power device can be integrated with an N channel power device conveniently. Simultaneously, a drift region of the SOI-based PMOSFET power device is formed by injecting a P type well region on the surface of an N type SOI semiconductor layer of the N type SOI rib, and in the reverse blocking state, the electric potential of the N type SOI semiconductor layer is high raised to perform two-dimensional exhausting for the P type drift region to generate a reduced surface electric field (RESURF) effect, accordingly puncture voltage and drift region concentration of the device are effectively improved, and on-resistance is greatly reduced. In addition, the SOI-based PMOSFET power device bears transverse pressure drop through a medium trough, can achieve high puncture voltage with small device transverse size, and accordingly can effectively reduce the transverse size.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and relates to SOI (Semiconductor On Insulator, semiconductor on an insulating layer)-based P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, Metal-Oxide-Semiconductor Field Effect Transistor) power device. Background technique [0002] P-channel MOSFET (hereinafter referred to as PMOSFET) is a field effect transistor that uses holes as conduction carriers. Because in silicon semiconductors, the mobility of holes is much smaller than that of electrons, so under the same doping concentration and structure size, the on-resistance of PMOSFET is much greater than that of N-channel MOSFET (hereinafter referred to as NMOSFET). resistance, which makes NMOSFETs more widely used and favored by people. However, because the application of PMOSFET in CMOS integrated circuits can greatly simplify the circuit, PMOSFET is still an irreplaceable and indispensable device. ...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06
Inventor 罗小蓉罗尹春周坤范叶王骁玮范远航蔡金勇张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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