Multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology

Abstract

The invention discloses a multilayer line manufacturing process of wafer-level micro electromechanical system chip encapsulation technology. The process comprises the following flows of: pre-processing, wafer thinning, exposure and development, etching, insulating layer coating, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching, insulating layer coating and exposure and development, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching, N (N is more than or equal to 0) times (insulating layer coating and exposure and development, laser drilling, copper sputtering, chemical copper plating pretreatment, chemical copper plating, electric copper plating, exposure and development, copper etching), acid chemical nickel plating, chemical cyanide gilding, solder mask coating and exposure and development, BGA forming, and subsequent cutting, testing and packing. The process for forming a multilayer mutual conduction line effectively deals with product size reduction and line denseness, and improves the yield of products.

Description

technical field [0001] The invention relates to the field of manufacturing technology of circuits and welding pads in wafer-level MEMS chip through-silicon hole packaging technology products. Background technique [0002] At present, in the manufacturing process of wafer-level micro-electromechanical system (English abbreviation: MEMS) chip through-silicon via (English abbreviation: TSV) packaging technology, single-layer wiring is generally used, and the conductive block inside the wafer is exposed through the previous process (English abbreviation: TSV). Abbreviation: pad), aluminum sputtering, photoresist coating exposure development, nickel plating, photoresist removal, aluminum removal of photoresist layer, etching, nickel gold plating, solder mask coating exposure development, solder paste printing , reflow soldering and other processes to electrically interconnect the inside and outside of the wafer, and produce the required lines and ball grid array (English abbrevia...

AI Technical Summary

Problems solved by technology

Generally, the line width and the line or pad spacing are in the range of 40-100 microns, and the spacing between the edges of the pads is mostly about 300 microns, and three to four lines are electrically interconnected from the inside and outside of the wafer within the spacing of about 300 microns. And it meets the requirements of line width and line spacing. Under the current technical conditions, the operation faces many problems, such as the etching is not clean during etching, the problem of short circuit, etc. It is extremely difficult to avoid bad problems, which directly affects the output and yield. The design of customer lines sometimes requires three or more lines to be drawn from the space between the edges of the pads, which makes the production process face difficulties, and the yield cost advantage is no longer there, thus restricting the competitiveness of the product