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Two-step deposition tchnique for dielectric layer between metalic wires

A metal wire and dielectric film technology, which is applied in the field of two-step deposition process of dielectric film between metal interconnection lines, can solve the problems of long deposition time, low output of HDPCVD equipment, Al voids, etc., and achieve shortened processing time, The effect of shortening the processing cycle and increasing the output

Inactive Publication Date: 2004-10-27
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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  • Summary
  • Abstract
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  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Usually, one-step deposition is used in the HDPCVD process. For example, the HDPCVD process with a D / S (deposition / sputtering) of 3.0 and a deposition thickness of 1000nm have at least two disadvantages: the deposition time is too long, The output of HDPCVD equipment is low; the temperature may be too high to cause Al voids

Method used

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Examples

Experimental program
Comparison scheme
Effect test

example 1

[0010] Example 1, put the etched and cleaned silicon wafer into the HDPCVD deposition chamber (such as the Ultima chamber produced by Applied Materials), and deposit it with a two-step method menu: that is, 1) D / S (deposition / sputtering) was 3.4, deposited 450 nm; 2) D / S (deposition / sputtering) was 6.0, deposited 450 nm; its total thickness was 900 nm. These two steps of deposition are completed continuously in the cavity at one time.

example 2

[0011] Example 2, the conditions of two-step method deposition: 1) D / S (deposition / sputtering) is 3.3, deposition 400nm; 2) D / S (deposition / sputtering) is 5.2, deposition 450nm; The total thickness is 850 nm.

example 3

[0012] Example 3, two-step deposition conditions: 1) D / S (deposition / sputtering) is 3.5, deposition 500nm; 2) D / S (deposition / sputtering) is 5.8, deposition 350nm; The total thickness is 850 nm.

[0013] Example 4, the conditions of two-step method deposition: 1) D / S (deposition / sputtering) is 3.4, deposition 450nm; 2) D / S (deposition / sputtering) is 6.0, deposition 350nm; The total thickness is 800nm.

[0014] The above examples can effectively increase the throughput of the HDPCVD process and shorten the processing time of each silicon wafer by 20-30%.

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PUM

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Abstract

In order to raise yield of Chemical Vapor Deposition (CVD) of high-density plasma (HDP), HDPCVD technique is optimized. HDPCVD technique is utilized for space filling mainly. The invention is pointed to space filling in A / R ratio between depth and width of groove as less than or equal to 2.3. the invention shortens deposition time 20-30% so as to raise yield of HDPCVD device.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and in particular relates to a two-step deposition process of a dielectric film between metal interconnection lines. Background technique [0002] From an international point of view, it has now entered the mainstream 0.13μm copper process, and developed 0.09μm or more advanced technology; but the mainstream of domestic IC large-scale production line technology is 0.25μm process, although a few manufacturers have entered 0.18μm or more advanced technology; From the requirements of the IC foundry (Foundry), it is not an easy task to establish a stable 0.25μm process platform, that is, as long as the product is a 0.25μm process, the IC foundry can produce it. [0003] However, due to the continuous update and diversification of products, as well as the various requirements of customers, it is necessary to continuously study and solve various new pro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/31H01L21/768
Inventor 缪炳有
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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