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Power semiconductor chip packaging structure capable of realizing low-temperature bonding and high-temperature service

A technology for power semiconductors and high-temperature service. It is applied in the direction of semiconductor devices, semiconductor/solid-state device components, and electrical solid-state devices. It can solve problems such as high hardness, unfavorable device reliability, and high brittleness, and achieve good solderability of the coating. The effect of delaying the turbidity of the plating solution and preventing the formation of dendrites

Pending Publication Date: 2022-05-27
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In Babbitt alloys, SnSb IMCs are wear-resistant phases with high hardness and high brittleness. Therefore, although SnSb IMCs in the packaging structure meet the needs of high-temperature packaging, it is not conducive to the reliability of the device during service.
The Chinese invention patent (CN200810028182.8) proposes a solder alloy composed of Sn, Sb, Cu and a small amount of alloying elements. This patent also has the problem of service reliability

Method used

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  • Power semiconductor chip packaging structure capable of realizing low-temperature bonding and high-temperature service
  • Power semiconductor chip packaging structure capable of realizing low-temperature bonding and high-temperature service
  • Power semiconductor chip packaging structure capable of realizing low-temperature bonding and high-temperature service

Examples

Experimental program
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Effect test

Embodiment 1

[0032] In the traditional package structure, the gold Ti / Ni / Au layer on the back of the chip and the surface of the Cu layer on the substrate are plated with Co by electroplating. First, the surface of the plated sample was cleaned with dilute sulfuric acid, deionized water and acetone with a concentration of 30 vol%. The low-stress Co electroplating solution was prepared according to the "Electroplating Manual", and the solution composition was: cobalt sulfamate 450g / L, formamide 30mL / L, sodium lauryl sulfate 0.4g / L, saccharin 1.0g / L . Electroplating temperature 40℃, current density 4.0A / dm 2, control the plating time so that the thickness of the Co coating is about 5 μm. The surface of the electroplated Co layer was washed with deionized water and blown dry, and the Sn plating treatment was further performed. Preferably, the components of the electroplating solution are selected to be composed of 20 g / L of stannous sulfate, 90 g / L of sulfuric acid, 3.0 g / L of ferrous sulf...

Embodiment 2

[0034] In the traditional package structure, the gold Ti / Ni / Au layer on the back of the chip and the surface of the Cu layer on the substrate are plated with Co by electroplating. First, the surface of the plated sample was cleaned with dilute sulfuric acid, deionized water and acetone with a concentration of 30 vol%. The low-stress Co electroplating solution was prepared according to the "Electroplating Manual", and the solution composition was: cobalt sulfamate 450g / L, formamide 30mL / L, sodium lauryl sulfate 0.4g / L, saccharin 1.0g / L . Electroplating temperature 40℃, current density 4.0A / dm 2 , control the plating time so that the thickness of the Co coating is about 10 μm. The surface of the electroplated Co layer was washed with deionized water and blown dry, and the Sn plating treatment was further performed. The components of the electroplating solution were selected as 10g / L of stannous sulfate, 100g / L of sulfuric acid, 1.0g / L of ferrous sulfate, 0.5g / L of antimony po...

Embodiment 3

[0036] In the traditional package structure, the gold Ti / Ni / Au layer on the back of the chip and the surface of the Cu layer on the substrate are plated with Co by electroplating. First, the surface of the plated sample was cleaned with dilute sulfuric acid, deionized water and acetone with a concentration of 30 vol%. The low-stress Co electroplating solution was prepared according to the "Electroplating Manual", and the solution composition was: cobalt sulfamate 450g / L, formamide 30mL / L, sodium lauryl sulfate 0.4g / L, saccharin 1.0g / L . Electroplating temperature 40℃, current density 4.0A / dm 2 , control the plating time so that the thickness of the Co coating is about 10 μm. The surface of the electroplated Co layer was washed with deionized water and blown dry, and the Sn plating treatment was further performed. Preferably, the components of the electroplating solution are selected to be composed of 50 g / L of stannous sulfate, 50 g / L of sulfuric acid, 1.0 g / L of ferrous su...

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Abstract

The invention discloses a power semiconductor chip metal layer structure capable of realizing low-temperature bonding and high-temperature service, which is characterized in that on the basis of the traditional back gold layer Ti / Ni / Au of a chip, a metal Co layer and a metal Sn layer are respectively deposited through an electroplating method, and meanwhile, the metal Co layer is electroplated on the surface of a substrate copper layer to form a Co / Sn / Co sandwich structure. The electroplated Sn coating is compact in grain and has the advantages of being low in porosity and good in weldability, and the problems of cavities, organic matter residues and the like caused in the backflow process of a solder layer such as soldering paste or a soldering lug are solved.

Description

technical field [0001] The invention belongs to the technical field of packaging of power semiconductor chips, in particular to a power semiconductor chip packaging structure that can realize low-temperature bonding and high-temperature service. Background technique [0002] Power devices are the core of power conversion and circuit control in electronic devices, mainly including secondary boards, thyristors, MOSFETs, and IGBTs. Power devices have significant advantages in high voltage resistance, high current and fast response, but with the increase of energy density, the reliability of the device faces a severe test. For example, in the 3300V and above soldered IGBT power modules on the market, during a reflow, the soldering material of the chip soldering / DCB ceramic substrate is high melting point gold-tin solder or high lead solder (lead content is higher than 85%). For the selection of welding materials, on the one hand, the material needs to provide a certain mechanic...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L23/498
CPCH01L24/32H01L24/29H01L23/49811H01L2224/32503H01L2224/32151H01L2224/32221H01L2224/32225H01L2224/29111H01L2224/29157H01L2224/29147H01L2224/48091H01L2224/48139H01L2924/00014
Inventor 田爽张振越王波王剑锋黄卫杨中磊
Owner 58TH RES INST OF CETC
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