Wafer manufacturing process for preparing ILD insulating layer by using low-frequency radio-frequency plasma

Abstract

The invention discloses a wafer manufacturing process for preparing an ILD insulating layer by using low-frequency radio-frequency plasma. The wafer manufacturing process comprises the following stepsthat S1, the surface of a wafer is cleaned and then put into an RF plasma reactor, the edge of the wafer is fixed by using an annular clamp, and high-temperature gas is injected from a gap of a lowerelectrode to heat the bottom of the wafer, so that the wafer is kept at a certain temperature; S2, the RF plasma reactor is subjected to air exhaust through a vacuum pump, so that the interior of theRF plasma reactor is in a vacuum state, and then N2 is introduced to reach the reaction pressure; and S3, an organic precursor and O2 are introduced, the distance between electrode plates is controlled at the same time, a radio frequency power supply is turned on, and plasmas are generated between the electrodes through bombardment of the low-frequency RF generate so as to deposit the ILD insulating layer on the surface of the wafer. According to the wafer manufacturing process, TEOS and TMP gases are introduced into the low-frequency radio-frequency plasma, and are introduced into a reactioncavity with N2 as a carrier, and the compact ILD film with stable dopant bonding can be formed by utilizing the bombardment of the low-frequency radio-frequency plasma and a relatively high reactiontemperature at a relatively high temperature.

Description

technical field [0001] The invention relates to the field of wafer packaging, in particular to a wafer manufacturing process for preparing an ILD insulating layer using low-frequency radio frequency plasma. Background technique [0002] The dielectric layer is an electrical insulation layer between the silicon device and the metal layer and between the metal layer and the metal layer, also known as the interlayer dielectric ILD. The interlayer dielectric ILD includes SiO 2 , BPSG, PSG, Polymers, SiN 4 , Aerogels and low-k media, etc. The ILD of current power semiconductors (such as MOSFET, IGBT, PMIC, etc.) plays a very important role in the operation and reliability of the device. The overall insulation of the ILD must be perfect, and there must be no leakage during the working cycle of extremely high voltage / current There must be no pores in the insulating layer, and it must have sufficient density. At the same time, due to the consideration of heat dissipation of the c...

AI Technical Summary

Problems solved by technology

The ILD of current power semiconductors (such as MOSFET, IGBT, PMIC, etc.) plays a very important role in the operation and reliability of the device. The overall insulation of the ILD must be perfect, and there must be no leakage during the working cycle of extremely high voltage / current There must be no pores in the insulating layer, and it must have sufficient density. At the same time, due to the consideration of heat dissipation of the components, high-power components should not be covered with a thick protective film on the metal layer. Therefore, the ILD itself must have the ability to resist the boundary moisture and Na + 、K + The ability of active ions, that is, after ILD is densified, it can block water vapor and have P bonds to capture active ions such as Na+ or K+, without diffusing into the transistor area and affecting the operation of the transistor

[0003] At present, the deposition method of Ozone and TEOS of APCVD or SACVD is generally used for interlayer dielectric ILD, but the above-mentioned process has the following disadvantages: (1) the film is very loose and porous, and the density is not enough; External diffusion; (3) The dopant bond is unstable, accumulates on the surface of the film after the high temperature step, and diffuses to the crystal matrix

If the traditional PETEOS process is used, the film formed by the high-frequency radio frequency plasma is also very loose, the P dopant bonding is unstable and the stress is high, and it is easy to produce gaps after the high temperature step

If the LPTEOS (low pressure TEOS CVD) process is used, the ILD film at high film forming temperature (>750°C) is relatively dense, and the dopant is also very stable. However, due to the vapor deposition process in the LPTEOS wet heating furnace tube, there will be Deposits are also formed on the round side and back. In the subsequent thinning process, when the back is ground, the LPTEOS film on the side wall is easy to break and fall off due to stress changes, resulting in gaps in the manufacturing process, which are not easy to solve

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