Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. According to the invention, a shielding gate field effect transistor is arranged in the cell region of the semiconductor device, a super-barrier rectifier is arranged in the non-cellular region, and the upper dielectric layer and the lower dielectric layer of the second dielectric layer in the super-barrier rectifier can be smoothly connected based on a beak structure, so that a tip structure between the upper dielectric layer and the lower dielectric layer of the second dielectric layer is avoided, and the problem that leakage current is easily caused due to the fact that the thickness of the bottom of the upper dielectric layer of the second dielectric layer is too thin can be effectively solved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a forming method thereof. Background technique [0002] A shielded gate field effect transistor (Shielded Gate Trench, SGT) is more conducive to the flexible application of semiconductor integrated circuits because of its low gate-to-drain capacitance Cgd, very low on-resistance, and high withstand voltage performance. Specifically, in the shielded gate field effect transistor, by setting the shielding electrode below the gate electrode, the gate-to-drain capacitance can be greatly reduced, and the drift region of the shielded gate field effect transistor also has a relatively high impurity carrier Concentration, can provide additional benefits to the breakdown voltage of the device, which can reduce the on-resistance accordingly. [0003] Furthermore, for semiconductor devices with shielded gate field effect transistors, in order to achieve fas...

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Problems solved by technology

However, precisely because the required thickness of the upper dielectric layer 22C in the rectifying region 10C is relatively thin, incomplete oxidation often occurs at the corner position 20C (for example, the sidewall of the corner position 20C is difficult to full contact with oxygen), which leads to too small thickness of the oxide layer at the corner position 20C, which will cause the leakage current problem of the device

[0013] In addition, since the upper dielectric layer 22A in the cell region 10A affects the device performance of the shielded gate field effect transistor, and the upper dielectric layer 22C in the rectification region 10C affects the turn-on performance of the super-barrier rectifier, the two usually need to be set with different thicknesses To meet the needs of respective devices, for this reason, when preparing the two upper dielectric layers in different steps, generally two photomasks are used and two photolithography processes are performed, the preparation process is complicated, the cost is high, and When the photoresist is formed in the photolithography process to cover one of the trenches, it is also easy to cause the problem of photoresist remaining in the trench

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