Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

High-dielectric-constant gate dielectric material and preparation method thereof

A technology with high dielectric constant and gate dielectric, applied in nanotechnology, circuits, electrical components, etc. for materials and surface science, can solve problems such as poor interface quality, easy leakage, and poor reliability, and reduce the dielectric interface. The effect of increasing the density of states, improving the quality of the interface, and reducing the density of states at the interface

Pending Publication Date: 2020-09-08
GLOBAL ENERGY INTERCONNECTION RES INST CO LTD +2
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Therefore, the technical problem to be solved in the present invention is to overcome defects such as poor interface quality, easy leakage, and poor reliability of gate dielectric materials in the prior art, thereby providing a high dielectric constant gate dielectric material and its preparation method

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High-dielectric-constant gate dielectric material and preparation method thereof
  • High-dielectric-constant gate dielectric material and preparation method thereof
  • High-dielectric-constant gate dielectric material and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0088] This embodiment provides a method for preparing a high dielectric constant gate dielectric material, the flow chart of which is shown in figure 1 , include,

[0089] (1) Pretreatment of silicon carbide epitaxial wafers

[0090] The silicon carbide epitaxial wafer 110 includes a substrate 101 and an epitaxial layer 102, such as figure 2 As shown, the substrate is (0001) n-type nitrogen-doped 4H-SiC with a 4 inclination angle, the thickness is 350 μm, and the resistivity is 0.001Ω·cm; the epitaxial layer is nitrogen-doped 6H-SiC, and the crystal orientation is the same as that of the substrate Same, the doping concentration is 1×10 15 cm -3 , with a thickness of 12 μm;

[0091] Perform the first cleaning on the epitaxial wafer, the first cleaning includes standard Piranha process cleaning, RCA process cleaning and DHF process cleaning; after cleaning, perform ion implantation process on the silicon carbide epitaxial wafer, so that the well region 111 and the base con...

Embodiment 2

[0099] This embodiment provides a method for preparing a high dielectric constant gate dielectric material, including:

[0100] (1) Pretreatment of silicon carbide epitaxial wafers

[0101] Such as Figure 8 As shown, a silicon carbide epitaxial wafer 210 includes a substrate 201, a first epitaxial layer 202, a second epitaxial layer 203, and a third epitaxial layer 204. The first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are formed on the substrate crystal grow in the same crystal direction on the surface; wherein, the substrate 201 is (0001) n-type nitrogen-doped 4H-SiC with 4 tilt angles, the resistivity is 0.001Ω·cm, and the thickness is 350 μm; the first epitaxial layer 202 is n-type nitrogen-doped 4H-SiC with the same crystal orientation as the substrate, with a doping concentration of 5×10 15 cm -3 , with a thickness of 12 μm; the second epitaxial layer 203 is p-type aluminum-doped 4H-SiC with the same crystal orientation as the subst...

Embodiment 3

[0110] This embodiment provides a method for preparing a high dielectric constant gate dielectric material, including:

[0111] (1) Pretreatment of silicon carbide epitaxial wafers

[0112] The silicon carbide epitaxial wafer 310 includes a substrate 301 and an epitaxial layer 302, such as Figure 14 As shown, the substrate is semi-insulating undoped (0001) 4H-SiC with 4 dips, and the resistivity is greater than 10 5 Ω cm, the thickness is 350 μm, the epitaxial layer is n-type nitrogen-doped 4H-SiC, the crystal orientation is the same as that of the substrate, and the doping concentration is 5×10 15 cm -3 , the thickness of the epitaxial layer is 12 μm;

[0113] Perform the first cleaning on the epitaxial wafer 310, the first cleaning includes standard Piranha process cleaning, RCA process cleaning and DHF process cleaning; the cleaned silicon carbide epitaxial wafer is subjected to ion implantation process, so that the well region 311 and base contact are formed in the epi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention belongs to the technical field of semiconductor device preparation, and particularly relates to a high-dielectric-constant gate dielectric material and a preparation method thereof. Thehigh-dielectric-constant gate dielectric material comprises an AlN layer, an AlOxNy layer and an Al2O3 layer which are sequentially stacked from bottom to top. The gate dielectric layer has relativelyhigh interface quality, interface state density and high reliability, and meanwhile, the gate dielectric layer is relatively good in uniformity and relatively few in current leakage problem.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device preparation, and in particular relates to a high dielectric constant gate dielectric material and a preparation method thereof. Background technique [0002] As a model of the third-generation wide-bandgap semiconductor material, SiC semiconductor material has a wider 4H~SiC (theoretical value is 3.2eV), higher breakdown electric field strength (2.2MV / cm), higher high saturation electron migration Rate (2.0×10 7 cm / s), high thermal conductivity (5.0W / cm K), excellent physical and chemical stability and other characteristics, suitable for the manufacture of high power, high voltage, high operating temperature, high operating frequency power semiconductor devices Material. [0003] Compared with other compound semiconductor materials, SiC can be naturally oxidized like silicon to form dense high-quality SiO 2 On the one hand, the SiC process has higher process compatibility and matur...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L29/51H01L21/285H01L21/28B82Y40/00B82Y30/00B82Y10/00
CPCH01L29/513H01L21/285H01L21/28008H01L29/517H01L29/518B82Y10/00B82Y30/00B82Y40/00
Inventor 夏经华张文婷田丽欣安运来田亮查祎英杨霏吴军民
Owner GLOBAL ENERGY INTERCONNECTION RES INST CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com