Neutral network processor based on data compression, design method and chip

Abstract

The invention provides a neutral network processor based on data compression, a design method and a chip. The processor comprises at least one storage unit used for storing operating instructions and data participating in calculation, at least one storage unit controller used for controlling the storage unit, at least one calculation unit used for executing calculation of a neutral network, a control unit connected with the storage unit controllers and the calculation units and used for acquiring instructions stored by the storage unit through the storage unit controllers and analyzing the instructions to control the calculation units, and at least one data compression unit used for compressing data participating in calculation according to a data compression storage format. Each data compression unit is connected with the corresponding calculation unit. Occupancy of data resources in the neutral network processor is reduced, the operating rate is increased, and energy efficiency is improved.

Description

technical field [0001] The invention relates to the field of hardware acceleration for neural network model calculation, in particular to a data compression-based neural network processor, design method and chip. Background technique [0002] Deep learning technology has developed rapidly in recent years. Deep neural networks, especially convolutional neural networks, have achieved a wide range of applications in image recognition, speech recognition, natural language understanding, weather prediction, gene expression, content recommendation, and intelligent robots. [0003] The deep network structure obtained by deep learning is an operational model, which contains a large number of data nodes, each data node is connected to other data nodes, and the connection relationship between each node is represented by weight. With the continuous improvement of the complexity of the neural network, the neural network technology has many problems in the actual application process, su...

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Literature "Albericio J, Judd P, Hetherington T, et al.Cnvlutin: ineffective-neuron-free deep neural network computing[C] / / Computer Architecture(ISCA),2016ACM / IEEE 43rd Annual International Symposium on.IEEE,2016:1 -13." By providing large-scale storage units on the chip to achieve large-scale parallel computing and based on this, the compression of data elements is realized, but this method relies on large-scale on-chip storage units to meet its parallel computing needs, Not suitable for embedded devices; "Chen Y H, Emer J, Sze V.Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks[J].2016." Data reuse and power by sharing data and weights The gating method closes the calculation of data 0, which can effectively improve energy efficiency, but this method can only reduce the power consumption of the operation and cannot skip elements with a value of 0 to speed up the calculation.

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