Fin-type field effect transistor forming method

Abstract

The invention discloses a fin-type field effect transistor forming method, and the method comprises the steps: providing a substrate, wherein the surface is provided with a plurality of separated fin parts; forming a separation layer on the surface of the substrate, wherein the top of the separating layer is lower than the top of the fin parts, and covers the surface of a part of side walls of the fin parts; forming a side wall layer covering the surfaces of the side walls of the fin parts, and exposing the top surfaces of the fin parts; carrying out the selective nitrogen treatment of the tops of the fin parts, and enabling the fin parts at a certain thickness to be converted into a semiconductor nitridation layer; carrying out the etching of the semiconductor nitridation layer through employing a wet etching method, so as to form openings between the adjacent side wall layers and the remaining fin parts; and placing stress layers in the openings. The method improves the flatness of the bottom of the opening, improves the quality of the formed stress layers, and optimizes the electrical performances of a fin-type field effect transistor.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor. Background technique [0002] With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following Moore's Law continues to decrease. In order to adapt to the reduction of process nodes, the channel length of MOSFET field effect transistors has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip and increasing the switching speed of the MOSFET field effect tube. [0003] However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control ability of the gate to the channel becomes worse, and the gate voltage pinches off (pinchoff) the channel. The difficulty is also increasin...

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Problems solved by technology

[0007] However, the quality of the stress layer formed by the prior art is poor, resulting in poor electrical performance of the FinFET

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