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Integration method of vertical nano-wire transistor

An integration method, nanowire technology, applied in nanotechnology, nanotechnology, nanotechnology for information processing, etc., can solve problems such as limiting the improvement of device performance and difficult to use gate-last process, to improve consistency, avoid Etch damage and performance improvement effect

Active Publication Date: 2016-03-02
PEKING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] This integration scheme is difficult to use the gate-last process, which limits the improvement of device performance;

Method used

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  • Integration method of vertical nano-wire transistor
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  • Integration method of vertical nano-wire transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0094] The CMOS integration of bulk silicon vertical nanowire devices with a diameter of 6nm can be realized according to the following steps (the structure parameters are set according to the High-Performance device of the "11 / 10nm" technology generation in ITRS-2013):

[0095] 1) Form a double well (Nwell / Pwell), SiO on a (100) bulk silicon substrate according to the published bulk silicon process 2 Shallow Trench Isolation (STI), the surface is planarized by Chemical-Mechanical Polishing (CMP), and the substrate surface retains 50nmSiO 2 ,Such as figure 2 Shown

[0096] 2) Form the epitaxial window of the active area under the device by photolithography and anisotropic etching;

[0097] 3) P+ heavily doped active regions (as the source / drain terminals of PMOS) are formed on the Nwell by in-situ doped epitaxial processes, and N+ heavily doped active regions (as the source of NMOS) are formed on the Pwell. / Drain), such as image 3 Shown

[0098] 4) Deposit 5nmSiO sequentially by AL...

Embodiment 2

[0121] According to the following steps, the hybrid integration of vertical nanowire devices (such as Si-NMOS and Ge-PMOS) with a diameter of 4.5nm with two material channels on an SOI substrate can be realized (the structure parameters are based on ITRS-2013 "8 / 7nm" High-Performance device of technology generation to set):

[0122] 1) Epitaxy 20nm GeSi on a (100) SOI substrate, and do N+ and P+ respectively to form the lower active region of the device (as the source / drain of the device);

[0123] 2) The isolation of the active area under the N / P device is realized by photolithography and etching, such as Figure 19 Shown

[0124] 3) Through LPCVDSiO 2 STI is formed, and the surface is planarized by CMP to expose the upper surface of the heavily doped active region;

[0125] 4) Deposit 3nmSiO sequentially by ALD 2 (As the SDE mask layer 1, its thickness defines the length of the device's source and drain extension SDE is 3nm), 14nmSi3N4 (fake gate layer, its thickness defines the cha...

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Abstract

The invention discloses an integration method of a vertical nano-wire transistor, and belongs to the field of field effect transistor logic devices in CMOS ULSI. According to the method, graphical extension is combined with a sidewall alternative gate to realize integration of the vertical nano-wire transistor. Compared with a present method in which vertical nano wire channels are formed by etching, the sectional area and morphology of the channel of the control device can be accurately controlled, the characteristic consistency of the device is improved, damage caused by etching in the channel formation process is avoided, and the device performance is improved.

Description

Technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit manufacturing, and relates to a method combining patterned epitaxy and sidewall replacement gates to achieve vertical nanowire transistor integration. Background technique [0002] When the semiconductor device enters the 22nm technology generation, the horizontal channel three-dimensional multi-gate device (Multi-gateMOSFET, MuGFET) represented by the fish fin field effect transistor (FinFET), with its outstanding ability to suppress the short channel effect, high integration density , Compatibility with traditional CMOS technology and other advantages, has become the mainstream of semiconductor devices. [0003] However, when moving toward a smaller size technology node, horizontal channel three-dimensional multi-gate devices are faced with challenges such as difficulty in reducing the spacing of contact holes (limiting the increase in integration density) and gate etching ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238
CPCH01L21/823807H01L21/823885H01L29/401B82Y10/00B82Y40/00H01L29/4236H01L29/66439H01L29/775H01L29/66666H01L29/7827H01L29/66545H01L29/0676H01L21/823814H01L21/823828H01L21/823878H01L21/823871
Inventor 黎明杨远程陈珙樊捷闻张昊黄如
Owner PEKING UNIV
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