Accessing and memorizing method and accessing and memorizing device of message type DRAM (Dynamic Random Access Memory) module
A message-based memory and memory module technology, applied in static memory, response error generation, redundant code error detection, etc., can solve the problems of power loss, lack of flexibility, etc., and achieve the effect of low power consumption
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Embodiment 1
[0029] Please refer to figure 1 , an embodiment of the present invention provides a memory access device for a message-based memory module. The device can be deployed in the peripheral control circuit of the memory module, and can also be deployed in the memory controller; the memory controller can be integrated in a central processing unit (Central Processing Unit, CPU) or integrated on a computer motherboard.
[0030] The memory module may specifically be a DIMM, and the DIMM includes multiple DRAMs. In this paper, it is assumed that the bit width of DRAM is N bits, N is equal to the nth power of 2, and n is a positive integer; the burst length (Burst Length, BL) of DRAM is Q, and Q is a positive integer, preferably Q is equal to several times of 2 Square, for example, it is equal to 4 or 8; assuming that DIMM includes (M+2) blocks of DRAM, (M×N) is the bit width of the entire memory module, because the bit width (M×N) of a computer memory module is generally 2 A number of...
Embodiment 2
[0065] Please refer to image 3 , the embodiment of the present invention also provides a memory access method of a message-based memory module. The method is executed by a peripheral control circuit or memory controller of the memory module, specifically the memory access device as described in Embodiment 1 deployed in the peripheral control circuit or memory controller. The memory module includes (M+2) blocks of dynamic random access memory (DRAM), M is equal to the m power of 2, and m is a positive integer; the memory stored in each block of DRAM can be accessed within one read and write cycle The data is called single-chip burst cluster SCBC, and the collection of data stored in all DRAMs that can be accessed in the same read and write cycle forms a memory row.
[0066] The methods include:
[0067] 210. Store the SCBC to be stored in the current read-write cycle into the corresponding DRAM and locate it in the current memory row, and the DRAM used to store the SCBC does...
Embodiment 3
[0080] The embodiment of the present invention also provides a memory control system.
[0081] In one embodiment, as Figure 4a As shown, the system includes a message memory module 310, and the memory module 310 includes a peripheral control circuit 3101 and (M+2) blocks of DRAM 3102;
[0082] Among them, M is equal to the m power of 2, and m is a positive integer; the data stored in each DRAM that can be accessed within one read and write cycle is called single-chip burst cluster SCBC, and the data stored in all DRAMs can be stored in the same The collection of data accessed during a read / write cycle forms a memory row. The memory controller can be integrated on the main board of the computer or in the CPU of the computer.
[0083] The peripheral control circuit performs the following steps:
[0084]Store the SCBC to be stored in the current read and write cycle into the corresponding DRAM and be located in the current memory row, and the DRAM used to store the SCBC does ...
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