Super-junction device and manufacturing method thereof

Abstract

The invention discloses a super-junction device. A P type semiconductor thin layer is divided into two layers; one layer at the bottom is formed by a P type ion implantation zone; and the other layer at the top is formed by P type silicon filling a deep trench. The depth of the whole P type thin layer is decided by the longitudinal distance between the bottom surface of the bottom layer and the top surface of the top layer, thereby eliminating the influence on the depth of the P type thin layer by the depth change of the deep trench, realizing precise controlling of the depth of the P type thin layer and improving uniformity of the depth, and enhancing the breakdown voltage of the device. The depth changing range of the deep trench is determined by the depth the P type ion implantation zone of the bottom layer, thereby substantially expanding the process window of the deep trench, reducing the complexity of the process and the process cost, and meeting the requirement of continuous improvement of the carrier concentration of the P type semiconductor thin layer and the N type semiconductor thin layer. The N type epitaxial layer with high concentration can be used and a super-junction device with lower-ratio on resistance can be obtained. In addition, the invention also discloses a manufacturing method of the super-junction device.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device; the invention also relates to a manufacturing method of the super junction device. Background technique [0002] The super-junction device adopts a new withstand voltage layer structure, that is, a series of alternately arranged P-type and N-type semiconductor thin layers are used to make P-type and N-type semiconductor thin layers composed of P-type and N-type semiconductor thin layers in the off state at a lower voltage. The N-type region is depleted to achieve mutual compensation of charges, so that the P-type N-type region can achieve high breakdown voltage under high doping concentration, thereby obtaining low on-resistance and high breakdown voltage at the same time, breaking the traditional power device theory limit. [0003] MOSFET (Metal-Oxide-Semiconductor-Field-Effect Transistor) devices with a super-junction struc...

AI Technical Summary

Problems solved by technology

From the aspect of process, adopting the stepwise shrinking deep trench structure can expand some process windows and reduce the sensitivity of device characteristics to process, but because the N-type carriers of the conductivity type will be partially depleted by the adjacent P-type impurities, If the proportion of the depleted part of the N-type carriers is too high, the specific on-resistance of the device will increase, so the step of the deep trench cannot be too small; at the same time, the small step will bring The aspect ratio of the deep trench is improved, which increases the difficulty of the etching process and silicon filling process

Therefore, under the conditions of ensuring that the stepping of the deep trench meets the requirements and that the N-type semiconductor thin layer has a high concentration of carriers, the depth, width and inclination angle of the deep trench etching process are very high. requirements, the use of carrier concentrations higher than 1E16CM -3 When using an N-type epitaxial layer (corresponding to a conductivity of 1 ohm cm), for a device with a breakdown voltage of 600 volts or more, the depth of the deep trench, that is, the variation range of the P-type semiconductor thin layer 103 is required to be within 35 ± 1 micron Within, that is, the uniformity of the depth of the deep trench is required to be kept within the range of plus or minus 1 micron. This process window is too small, and it is impossible to maintain the variation range of the depth of the deep trench within 1 micron using the existing process and equipment conditions. Therefore, the existing process conditions cannot realize the alternating arrangement structure of P-type semiconductor thin layers and N-type semiconductor thin layers with high carrier concentration.

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