Semiconductor device preparing method

Abstract

The invention relates to a semiconductor device preparing method. The method comprises the following steps: a semiconductor substrate is provided, wherein the semiconductor substrate at least includes a gate structure; and grooves are formed in two sides of the gate and a SiGeB layer is grown in the grooves through epitaxial growth. The method is characterized in that B is doped in an in-situ manner while performing the epitaxial growth of the SiGe layer, and the epitaxial growth comprises two stages: the first stage is to increase the concentration of B in the SiGe layer to make the concentration of B in the SiGe layer reaches the peak concentration; and the second stage is to reduce the concentration of B in the SiGe layer so as to eliminate the short-channel effect. Through the method of the invention, not only a more flat doping tail contour can be acquired after the B doping process is performed so as to reduce the junction leakage phenomenon, and the method can skip the separate ion implantation process so as to make the stress in the channel region maintained; and but also the method can be used to make the doping concentration of B at channels is low so as to eliminate the short-channel effect to make prepared devices have good performances.

Description

technical field [0001] The invention relates to the field of semiconductors, and in particular, the invention relates to a method for preparing a semiconductor device. Background technique [0002] With the continuous development of semiconductor technology, the preparation of semiconductor devices tends to be miniaturized, and has been developed to the nanometer level, while the preparation process of conventional devices is gradually mature. The current method of preparing PMOS often includes the following conventional steps: firstly, a semiconductor substrate is provided, and then double wells, shallow trench isolation and polysilicon gate structures are formed on the semiconductor substrate. As the width of the gate continues to decrease, the gate The channel length under the structure is also continuously reduced. In order to effectively prevent the short channel effect, a lightly doped drain process (LDD) is introduced in the integrated circuit manufacturing process, a...

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Problems solved by technology

[0003] In order to obtain better performance, in the process of preparing PMOS, epitaxial SiGe is usually carried out in the source and drain regions of PMOS to apply compressive stress to the channel of the substrate, and then ion implantation is performed after epitaxial SiGe to obtain a higher doping concentration. In this process, high-energy, low-dose B (Boron) is usually used to dope its source and drain to form a doping tail profile to reduce the leakage at the junction, or to perform epitaxial growth of SiGe At the same time, B (Boron) doping is performed on the source and drain, and the gas flow rate and other parameters are adjusted to achieve sufficient doping concentration. However, after ion implantation or in-situ doping on the source and drain of PMOS SiGe It usually leads to strain relaxation of the device after annealing, and the strain relaxation will directly lead to the degradation of device performance

[0004] At the same time, the SiGe epitaxy or deposition method in the prior art is to directly deposit a SiGeB layer with a certain concentration gradient without providing SiGe crystal grains to reduce junction leakage current, but the SiGeB layer with a certain concentration gradient will cause boron Diffusion into channels and accelerated short channel effects

Secondary ion mass spectroscopy (SIMS) on the device obtained by the existing method found that the concentration of the in-situ doped boron concentration in the channel of the device is too high, so it is easy to accelerate the short channel effect

[0005] Therefore, in order to reduce the source-drain relaxation caused by ion implantation, the source-drain implantation step should be skipped as much as possible, but the control of B distribution at the junction becomes a challenge, and it is necessary to improve the current source-drain implantation method in PMOS, and at the same time eliminate Accelerated short channel effects in the presence of

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