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Volume rendering on shared memory systems with multiple processors by optimizing cache reuse

A shared memory and processor technology, applied in the field of image processing, can solve the problem that the drawing load will not be evenly distributed

Active Publication Date: 2013-10-23
SIEMENS HEALTHCARE GMBH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The problem encountered with this static load balancing approach is that the drawing load may not be evenly distributed across multiple processors

Method used

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  • Volume rendering on shared memory systems with multiple processors by optimizing cache reuse
  • Volume rendering on shared memory systems with multiple processors by optimizing cache reuse
  • Volume rendering on shared memory systems with multiple processors by optimizing cache reuse

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Embodiment Construction

[0212] refer to figure 1 , describes a volume rendering system, which includes an image acquisition system, such as a CT system or an MRT system, etc., and the image acquisition system is in figure 1 Indicated with the reference character CT. The modality is coupled to a server system via a network NW for images or volumetric rendering to be displayed on a monitor M.

[0213] figure 2 Shown is a rendering system 10 comprising several processors P 1 ,P 2 ,...P n . Generally, each processor P may include one or more processor cores C 1 、C 2 ,... C n , so it is called a multi-core system. Each core C accesses a cache 12 or a cache hierarchy having several caches 12 with different access properties. As multi-core processors become common and the number of on-die cores increases, a key processor design issue is for the on-die last-level cache LLC and thus for the algorithm with an efficient cache hierarchy in mind Hierarchy and strategy to reduce off-chip data misses an...

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Abstract

Present invention relates to a method, system and product for volume rendering of medical images on a shared memory system (10) implemented on a multi-socket mainboard with multiple multi-core processors (P) and multiple last level caches (LLC). The method comprises: - Decomposing the image space (MR) to be used for rendering in regions (Re); - Assigning two sockets (S) to each of the decomposed regions (Re) for the purpose of rendering; - Determining a tile enumeration scheme for a region (Re); - Rendering all tiles (T) of the plurality of tiles (T) within a region (Re) according to the determined tile enumeration scheme on the assigned two sockets (S) until the respective region (Re) is finished; - If a region (Re) is finished: Assigning the two sockets (S) to another region (Re); - If no region (Re) is left: Splitting an existing region of un-rendered tiles into sub-regions according to a splitting scheme and applying the steps recursively for the sub-regions.

Description

technical field [0001] The present invention relates to the field of image processing, in particular to volume rendering and in particular to methods for optimizing cache reuse by taking hardware architecture into account. [0002] Rapid visualization of large amounts of image data is a major problem in many fields of engineering and science such as medical technology image processing. Because of the size of modern voxel datasets, especially in medical imaging, huge memory accesses have to be made to compute all items of the volume dataset. Since the improvement in hardware computing capability brought about by increasing the number of computing cores due to parallelization is greater than the improvement in memory bandwidth and memory latency, for volume rendering algorithms, volume data memory access performance becomes the key to overall performance in many cases Constraints. Therefore, to achieve optimal performance, it is important to minimize the impact of memory acces...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06T1/60G06F12/0806
CPCG06F9/5066G06T15/005G06F9/5083G06T1/60G06T15/08G06T2210/52G06F12/0806
Inventor R.施奈德
Owner SIEMENS HEALTHCARE GMBH
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