High-drive-current III-V metal oxide semiconductor device

Abstract

The invention discloses a high-drive-current III-V metal oxide semiconductor device which comprises a single crystal substrate, a buffer layer, a quantum-well bottom barrier layer, a planar doped layer, a high-mobility quantum-well channel, an interface control layer, a high K gate dielectric, an elevated source / drain layer, a metal gate structure and a source / drain contact metal layer, wherein the buffer layer is formed on the upper surface of the single crystal substrate; the quantum-well bottom barrier layer is formed on the upper surface of the buffer layer; the planar doped layer is formed in the quantum-well bottom barrier layer; the high-mobility quantum-well channel is formed on the upper surface of the quantum-well bottom barrier layer; the interface control layer is formed on the upper surface of the high-mobility quantum-well channel; the high K gate dielectric and the elevated source / drain layer are formed on the upper surface of the interface control layer; the metal gate structure is formed on the high K gate dielectric; and the source / drain contact metal layer is formed on the elevated source / drain layer. According to the invention, a dangling bond on an MOS (metal oxide semiconductor) interface is passivated by using an interface control layer technology, thereby realizing the low interface state density, reducing the scattering of current carriers in the channel, improving the concentration of two-dimensional electron gas or two-dimensional hole gas in a channel layer, and satisfying the requirements of a high-performance III-V CMOS (complementary metal oxide semiconductor) technology.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a III-V group metal oxide semiconductor (MOS) device with a high driving current realized by adopting interface control layer, bottom barrier plane doping and raising source and drain, Applied to high-performance III-V MOS devices. Background technique [0002] When the complementary metal-oxide-semiconductor (CMOS) technology enters the 22nm technology node, it is difficult to improve device performance by scaling down. The use of new materials and new devices has become an important research direction to continue to improve the performance of CMOS devices. III-V semiconductor materials have become a hot topic in current research because of their high electron mobility. However, high-quality thermally stable gate dielectric materials have been the main obstacle for the application of III-V semiconductors in large-scale CMOS integrated circ...

AI Technical Summary

Problems solved by technology

However, the properties of this interface still cannot be compared with SiO 2 Compared with Si, the high-k gate dielectric material is directly grown on the surface of the high-mobility channel, and the high density of the MOS interface state will lead to a decrease in the carrier mobility of the channel.

In addition, the density of states in the conduction band of III-V semiconductor materials is relatively low, which also limits the improvement of the driving current of the device to a certain extent.

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