Fin field effect transistor and forming method thereof

Abstract

The invention discloses a fin field effect transistor and a forming method thereof. The forming method of the fin field effect transistor comprises: providing a semiconductor substrate, the surface of the semiconductor substrate being provided with a projection fin portion and a grid structure which is disposed on the fin portion and covers a part of the top portion and the side wall of the fin portion; forming a first dielectric layer covering the grid structure; forming a second dielectric layer covering the first dielectric layer, the dielectric constant of the second dielectric layer being smaller than the dielectric constant of the first dielectric layer; etching back the second dielectric layer, and forming a second side wall; and etching the first dielectric layer by taking the second side wall as a mask, and forming a first side wall, the first side wall being provided with a horizontal portion and a vertical portion, the part of the fin portion covered by the first side wall constituting a negative covering zone. According to the invention, the parasitic capacitance between the grid structure of the fin field effect transistor and the conductive plug of a source region and a drain region is small.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a fin field effect transistor and a forming method thereof. Background technique [0002] MOS transistors generate switching signals by regulating the current through the channel region by applying a voltage to the gate. With the development of semiconductor technology, the control ability of the traditional planar MOS transistor on the channel current becomes weaker, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a semiconductor fin protruding from the surface of the semiconductor substrate, and a gate structure covering part of the top and side walls of the fin, A source region and a drain region are located in the fins on both sides of the gate structure. [0003] But below the 20nm node, the thickness of the fin field effect transistor fin is extremely small, and the short channel...

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Problems solved by technology

[0005] However, in the prior art, the sidewalls of fin field effect transistors with negative cover regions are formed with high dielectric constant materials, which increases the parasitic capacitance between the gate electrode and the subsequently formed conductive plugs in the source region and drain region, affecting Transistor performance

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